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Preliminary Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Features
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Applications
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Multiplexes three STS-1 signals into a SONET STS-3 signal. Multiplexes three AU-3 signals into an SDH STM-1 (AU-4) signal via a TUG-3 construction. Demultiplexes three STS-1 signals from a SONET STS-3 signal. Demultiplexes three AU-3 signals from an SDH STM-1 (AU-4) signal via a TUG-3 deconstruction. High-speed microprocessor interface configurable to operate with most commercial microprocessors. Detects STS-3/STM-1 (AU-4) loss-of-signal (LOS) conditions. Detects STS-3/STM-1 (AU-4) out-of-frame and loss-of-frame (OOF/LOF) conditions. Provides an 8-bit bus interface at the STS-1/AU-3 rate. Provides a bit serial, nibble-wide, or byte-wide interface at STS-3/STM-1 (AU-4) rate. Provides STS-3/STM-1 (AU-4) selectable scrambler/descrambler functions and B1/B2/B3 generation/detection. Accepts bit rate, nibble rate, or byte rate highspeed clocks (155.52 MHz, 38.88 MHz, or 19.44 MHz, respectively). STS-3/STM-1 (AU-4) internal clock and data recovery. Meets type B jitter tolerance of ITU-T G.958. Accommodates 0.5 UI jitter up to 20 MHz. 155.52 MHz input reference clock for on-chip PLL. Has on-chip PLL for clock synthesis, requiring only one external resistor. No output clock drift in absence of data transitions once lock is acquired. STS-1 termination mode. -40 C to +85 C temperature range. 208-pin, shrink quad flat pack (SQFP) package. Complies with GR-253-CORE (12/95), G.707 (3/96), G.783(1/94).
SONET/SDH line termination equipment. SDH path origination and termination equipment. SONET/SDH add/drop multiplexers. SONET/SDH cross connects. SONET/SDH test equipment.
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Description
The TMUX03155 STS-3/STM-1 (AU-4) multiplexer device provides three modes of operation: STS-3, STM-1 (AU-4), and STS-1 modes. In STS-3 mode, the TMUX03155 device provides all of the functions necessary to multiplex and demultiplex up to three STS-1 signals to/from a SONET STS-3 signal. In AU-4 mode, the TMUX03155 provides the functionality to multiplex and demultiplex up to three AU-3 signals to/from an STM-1 (AU-4) signal. In STS-1 mode, the high-speed side of the TMUX03155 operates at 51.84 MHz and can be used for STS-1 termination and for accessing transport overhead in the SONET frame. On the STS-3/STM-1 (AU-4) side, the device can be configured for either a 1-bit serial data interface, a 4-bit parallel (nibble-wide) data interface, or an 8-bit parallel (byte-wide) data interface. This allows the device to drive an OC3 optical signal directly or to allow for modular growth in terminal or add/drop applications. On the STS-1/AU-3 side, the TMUX03155 device provides a bus mode that can communicate with up to three STS-1/AU-3 devices at 19.44 Mbits/s. The TMUX03155 is designed to interface with the Agere Systems Inc. TMPR28051 device, or equivalent, providing complete mapping/ unmapping from/to an STS-3/STM-1 (AU-4) signal for up to 84 DS1 or 63 E1 signals.
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Preliminary Data Sheet April 2001
Table of Contents
Contents Page
Features ................................................................................................................................................................... 1 Applications .............................................................................................................................................................. 1 Description ................................................................................................................................................................ 1 Nomenclature Assumptions ...................................................................................................................................... 7 Block Diagram ..........................................................................................................................................................7 Pin Information ......................................................................................................................................................... 9 Summary of I/O Pins .........................................................................................................................................15 Mode Control Signals (See Register Description on page 54.) ..............................................................................16 STS-1 Mode ...........................................................................................................................................................16 Transmit Direction Overview ..................................................................................................................................17 STS-1/AU-3 Bus Mode Input Retiming ..............................................................................................................17 Input Select Control ...........................................................................................................................................17 STS-1/AU-3 Inputs ............................................................................................................................................17 Out-of-Frame (OOF) and Loss-of-Frame (LOF) Monitoring ..............................................................................18 Descramble Enable/Disable ..............................................................................................................................18 Monitor B1 and B2 Errors ..................................................................................................................................19 H4 Multiframe and Pointer Monitor (AU-4 Mode Only) ......................................................................................19 STS-3 Generate ................................................................................................................................................20 Transport Overhead Access Channel (TOAC) Insert ........................................................................................23 STS-3/STM-1 (AU-4) Scramble Enable ............................................................................................................23 STS-3/STM-1 (AU-4) B1, B2, and B3 BIP Generation ......................................................................................23 STS-3/STM-1 (AU-4) Loopback Control ............................................................................................................23 STS-3/STM-1 (AU-4) Output Interface ..............................................................................................................23 Receive Direction Overview ...................................................................................................................................23 Input Retime ......................................................................................................................................................24 Clock and Data Recovery ..................................................................................................................................24 STS-3/STM-1 (AU-4) Framing ...........................................................................................................................24 Loss of Signal ....................................................................................................................................................24 Loopback Select Logic ......................................................................................................................................25 RSTS-3/STM-1 (AU-4) Frame Synchronous Descrambling (SONET/SDH) .....................................................25 TOAC Drop ........................................................................................................................................................25 B1, B2, and B3 Checking ..................................................................................................................................25 Monitoring Functions .........................................................................................................................................25 Pointer Interpretation .........................................................................................................................................25 Data Demultiplex and Conversion (AU-4 Mode Only) .......................................................................................26 STS-1/AU-3 Output Byte Control ......................................................................................................................26 B1 and B2 Generate ..........................................................................................................................................26 STS-1/AU-3 Output Scramble ...........................................................................................................................27 Output Selection Logic ......................................................................................................................................27 Output Data Formatter ......................................................................................................................................27 Maintenance Functions ..........................................................................................................................................27 Maintenance Functions Disabled During Failure Conditions .............................................................................28 Common Maintenance and Control Functions ..................................................................................................28 Transmit Functions ............................................................................................................................................30 Receive Functions .............................................................................................................................................38 Typical Uses ...........................................................................................................................................................45 Section and Line Termination Multiplex ............................................................................................................45 Add/Drop Multiplex ............................................................................................................................................46 Digital Cross Connect ........................................................................................................................................46 Microprocessor Interface ........................................................................................................................................47 Overview ...........................................................................................................................................................47 2 Agere Systems Inc.
Preliminary Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Table of Contents (continued)
Contents Page
Microprocessor Configuration Modes ................................................................................................................47 Microprocessor Interface Pinout Descriptions ...................................................................................................47 Microprocessor Interface Register Architecture ................................................................................................49 Register Description ..........................................................................................................................................54 I/O Timing ........................................................................................................................................................101 Absolute Maximum Ratings ..................................................................................................................................106 Handling Precautions ...........................................................................................................................................106 Operating Conditions ............................................................................................................................................107 Electrical Characteristics ......................................................................................................................................108 Timing Characteristics ..........................................................................................................................................110 Operational Timing ..........................................................................................................................................110 Outline Diagram ....................................................................................................................................................117 208-Pin SQFP .................................................................................................................................................117 Ordering Information .............................................................................................................................................118 DS01-194PDH Replaces DS00-213TIC to Incorporate the Following Updates ...................................................118
Agere Systems Inc.
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Preliminary Data Sheet April 2001
List of Figures
Contents Page
Figure 1. TMUX03155 Block Diagram ................................................................................................................... 8 Figure 2. Pinout of 208 SQFP Device ................................................................................................................... 9 Figure 3. SFEBE Location ................................................................................................................................... 33 Figure 4. Line Termination Multiplex ................................................................................................................... 45 Figure 5. Add/Drop Multiplex ............................................................................................................................... 46 Figure 6. Digital Cross Connect ........................................................................................................................... 46 Figure 7. MODE 1--Read Cycle Timing (MPMODE = 0, MPMUX = 0) ............................................................ 102 Figure 8. MODE 1--Write Cycle Timing (MPMODE = 0, MPMUX = 0) ............................................................. 102 Figure 9. MODE 2--Read Cycle Timing (MPMODE = 0, MPMUX = 1) ............................................................ 103 Figure 10. MODE 2--Write Cycle Timing (MPMODE = 0, MPMUX = 1) ........................................................... 103 Figure 11. MODE 3--Read Cycle Timing (MPMODE = 1, MPMUX = 0) .......................................................... 104 Figure 12. MODE 3--Write Cycle Timing (MPMODE = 1, MPMUX = 0) ........................................................... 104 Figure 13. MODE 4--Read Cycle Timing (MPMODE = 1, MPMUX = 1) .......................................................... 105 Figure 14. MODE 4--Write Cycle Timing (MPMODE = 1, MPMUX = 1) ........................................................... 105 Figure 15. Single-Ended Input Specification ..................................................................................................... 108 Figure 16. THSJ0J1V1I Signal Structure Definition ........................................................................................... 112 Figure 17. Interface Data Timing ....................................................................................................................... 115 Figure 18. Bus Interface Signals ....................................................................................................................... 116
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Agere Systems Inc.
Preliminary Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
List of Tables
Contents Page
Table 1. Pin Descriptions for the 208-Pin SQFP Package .................................................................................. 10 Table 2. Input/Output Summary .......................................................................................................................... 15 Table 3. Transmit Mode Control Signals ............................................................................................................. 16 Table 4. Receive Mode Control ........................................................................................................................... 16 Table 5. Input Select Control ............................................................................................................................... 17 Table 6. Expected STS-1/AU-3 Input Frame Format .......................................................................................... 18 Table 7. STS-3 Output Overhead Format ........................................................................................................... 20 Table 8. STM-1 (AU-4) Output Overhead Format ............................................................................................... 21 Table 9. STS-1/AU-3 Format and Overhead Control Summary .......................................................................... 26 Table 10. STS-1/AU-3 Output Select Control ...................................................................................................... 27 Table 11. Monitors Disabled During Failure Conditions ...................................................................................... 28 Table 12. SFEBE Values ..................................................................................................................................... 33 Table 13. G1 Byte--AU-4 Mode Only ................................................................................................................. 34 Table 14. PFEBE Values ..................................................................................................................................... 34 Table 15. Value Offset Load Values .................................................................................................................... 36 Table 16. Transport Overhead Byte Access--Transmit Direction ....................................................................... 36 Table 17. TTOAC Control Bits ............................................................................................................................. 37 Table 18. STS-1/AU-3 Overhead Control ............................................................................................................ 42 Table 19. Transport Overhead Byte Access--Receive Direction ........................................................................ 44 Table 20. Microprocessor Configuration Modes .................................................................................................. 47 Table 21. MODE [1--4] Microprocessor Pin Definitions ...................................................................................... 47 Table 22. Device-Level Register Map ................................................................................................................. 49 Table 23. Page 0--J1 Byte Insert and Monitor .................................................................................................... 51 Table 24. Page 1--Error Counters ...................................................................................................................... 52 Table 25. Page 2--BER Algorithm Parameters .................................................................................................. 53 Table 26. Register 0 (RO) ................................................................................................................................... 54 Table 27. Registers 1--3 (RO) ............................................................................................................................ 54 Table 28. Registers 4, 5: One-Shot Register 0 1 (R/W) .................................................................................. 54 Table 29. Register 6: Scratch Register (R/W) ..................................................................................................... 55 Table 30. Registers 7--15: Delta/Event (COR-RO) ............................................................................................ 55 Table 31. Registers 16--24: Mask Bits (R/W) ..................................................................................................... 60 Table 32. Registers 25--51: State Bits (RO) ....................................................................................................... 62 Table 33. Register 52: Mode Control (R/W) ........................................................................................................ 64 Table 34. Register 53: Low-Speed Transmit Common Signals (R/W) ................................................................ 65 Table 35. Register 54--59: Transmit Low-Speed Port Input Control (R/W) ........................................................ 66 Table 36. Registers 60, 61: Transmit High-Speed Clock/Port Control (R/W) ...................................................... 67 Table 37. Register 62: Transmit High-Speed Control Signals (R/W) .................................................................. 68 Table 38. Register 62, and Page 0, Registers 128--191: Transmit High-Speed J1 Insert (R/W) ....................... 69 Table 39. Register 62, 69: Transmit High-Speed Control Signals (R/W) ............................................................ 69 Table 40. Register 62, 66: Transmit High-Speed Control Signals (R/W) ............................................................ 69 Table 41. Registers 63--65: Trace/Growth Bytes (R/W) ..................................................................................... 69 Table 42. Register 66: Transmit F1 Data Byte (R/W) .......................................................................................... 70 Table 43. Registers 67 and 68: K1 and K2 Insert Bytes (R/W) ........................................................................... 70 Table 44. Register 69: Transmit Sync Status Byte (R/W) ................................................................................... 70 Table 45. Register 70: Path Signal Trace Byte (R/W) ......................................................................................... 70 Table 46. Register 71: Path User Channel Byte (R/W) ....................................................................................... 70 Table 47. Register 72: Path Growth Byte (R/W) .................................................................................................. 70 Table 48. Register 73: Tandem Connection Byte (R/W) ..................................................................................... 71 Table 49. Register 74: Transmit High-Speed Line RDI Insertion Inhibit Bits (R/W) ............................................ 71 Table 50. Register 75: Transmit High-Speed Path RDI Insertion Inhibit Bits (R/W) ............................................ 71 Table 51. Register 76: Transmit High-Speed Error Insert Control Parameters (R/W) ......................................... 72 Agere Systems Inc. 5
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Preliminary Data Sheet April 2001
List of Tables (continued)
Contents Page
Table 52. Register 77: Transmit High-Speed Error Insert Control Parameters (R/W) ......................................... 73 Table 53. Register 78: Transmit High-Speed Error Insert (R/W) ......................................................................... 73 Table 54. Register 79: Receive/Transmit TOAC Control (R/W) .......................................................................... 74 Table 55. Registers 80, 81: Transmit TOAC Control (R/W) ................................................................................ 75 Table 56. Register 83, 84: Transmit High-Speed STS-3/STM-1 Output Frame Offset (R/W) ............................. 77 Table 57. A1-1 Alignment Parameters ................................................................................................................ 80 Table 58. BITCNT Alignment Table ..................................................................................................................... 80 Table 59. Register 85: Receive High/Low-Speed Port Control (R/W) ................................................................. 81 Table 60. Register 86: Receive J1 and Receive Low-Speed Port Select Control (R/W) ..................................... 82 Table 61. Register 87: STS-1/AU-3 Receive Control Bits (R/W) ......................................................................... 82 Table 62. Register 88: STS-1/AU-3 Receive Low-Speed AIS Inhibit Control Bits (R/W) .................................... 83 Table 63. Registers 88, 89: STS-1/AU-3 Loss of Signal Detector (R/W) ............................................................ 83 Table 64. Register 90--95: Continuous N Times Detect (CNTD) Values (R/W) ................................................. 83 Table 65. Register 95: Continuous N Times Detect (CNTD) B1 Control Bit (R/W) ............................................. 85 Table 66. Register 96: Test Pattern Drop Control and Status ............................................................................. 86 Table 67. Register 97: Test Pattern Drop Error Counter (RO) ............................................................................ 86 Table 68. Register 98: Receive Low-Speed Overhead Control Bits (R/W) ......................................................... 86 Table 69. Register 99: Receive Low-Speed BIP Error Insert (R/W) .................................................................... 87 Table 70. Registers 100--102: Receive Low-Speed Overhead Control Bits (R/W) ............................................ 87 Table 71. Register 103: Receive Low-Speed L-RDI Inhibit Control (R/W) .......................................................... 88 Table 72. Registers 104--106: Receive Low-Speed C1 Byte (R/W) .................................................................. 88 Table 73. Registers 107--109: Receive Low-Speed F1 Byte (R/W) ................................................................... 88 Table 74. Registers 110--115: Receive Low-Speed K1, K2 Byte Insert (R/W) .................................................. 88 Table 75. Registers 116--118: Receive Low-Speed Pass Control (R/W) ........................................................... 89 Table 76. Register 127: Page Control Register (R/W) ........................................................................................ 90 Table 77. Page 0 - Registers 128--191: J1 Insert Parameters (R/W) ................................................................ 90 Table 78. Page 0 - Registers 192--255: J1 Monitor Bytes (RO) ......................................................................... 90 Table 79. Page 1 - Registers 128--133: STS-1/AU-3 B1 BIP Error Counters (RO) ........................................... 90 Table 80. Page 1 - Registers 134--140: STS-1/AU-3 B2 BIP Error Counters (RO) ........................................... 91 Table 81. Page 1 - Registers 141--142: STS-3/STM-1 (AU-4) B1 Error Count (RO) ......................................... 91 Table 82. Page 1 - Registers 143--145: STS-3/STM-1 (AU-4) B2 Error Count (RO) ......................................... 91 Table 83. Page 1 - Registers 146--151: STS-3/STM-1 (AU-4) B3 Error Count (RO) ......................................... 92 Table 84. Page 1 - Registers 152--163: STS-3/STM-1 (AU-4) Pointer Increment/Decrement Counter (RO) .... 92 Table 85. Page 1 - Registers 164--166: Receive High-Speed SFEBE Count (RO) ........................................... 92 Table 86. Page 1 - Registers 167--172: Receive High-Speed Path FEBE Count (RO) ..................................... 93 Table 87. Page 2 - Register 131 (R/W) ............................................................................................................... 93 Table 88. Page 2 - Registers 128--141 (R/W) .................................................................................................... 94 Table 89. Page 2 - Register 145 (R/W) ............................................................................................................... 97 Table 90. Page 2 - Registers 142--155 (R/W) .................................................................................................... 97 Table 91. Microprocessor Interface I/O Timing Specifications .......................................................................... 101 Table 92. Recommended Operating Conditions ............................................................................................... 107 Table 93. Power Measurements (VDD = 3.3 V, 23 xC) .................................................................................... 107 Table 94. Logic Interface Characteristics .......................................................................................................... 108 Table 95. LVDS Interface Characteristics ......................................................................................................... 109 Table 96. Input Clock Specifications ................................................................................................................. 110 Table 97. Input Timing Specifications ................................................................................................................ 111 Table 98. Output Clock Specifications ............................................................................................................... 113 Table 99. Output Timing Specifications ............................................................................................................. 114
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Agere Systems Inc.
Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Description (continued)
Automatic receive monitoring functions can be configured to provide an interrupt to the control system, or the device can be operated in a polled mode. Built-in loopback at both the STS-1/AU-3 and STS-3/ STM-1 (AU-4) interfaces provides maximum flexibility for use in a number of SONET/SDH products including path termination multiplexers, add/drop multiplexers, and digital cross connects. A high-speed microprocessor interface and full user programmability on STS-1/AU-3 to STS-3/STM-1 (AU4) slot insertion and drop provide maximum flexibility for I/O configuration.
Block Diagram
In the transmit direction, the device outputs a clock and sync and accepts bused data [7:0] and a parity signal from up to three devices. The device outputs one data bundle at the STS-3/STM-1 (AU-4) rate (clock, sync, data [7:0], and parity bit). A local clock and optional frame sync signal are needed for operation of the device. A transport overhead access channel (TOAC) is provided to allow overwriting of the transport overhead bytes in the output STS-3/STM-1 (AU-4) frame. In the receive direction, the device accepts one STS-3/ STM-1 (AU-4) bundle (clock, data, parity). Optional clock and data recovery is available on the STS-3/ STM-1 (AU-4) receive input. The device also accepts a loss-of-signal indication from an external source. The device outputs three STS-1/AU-3 signals over a bus interface (clock, data, J0 time, parity). The STS-3/STM1 (AU-4) input clock is used to clock this direction. A transport overhead access channel is provided for additional external monitoring of the incoming transport overhead of the STS-3/STM-1 (AU-4) frame. A pointer interpreter is provided to monitor path functions. The device also has loopback capabilities at the STS1/AU-3 and STS-3/STM-1 (AU-4) interfaces. In addition, the device supports STS-1 termination. An 8-bit microprocessor interface, JTAG control logic, and incircuit test capabilities are also provided.
Nomenclature Assumptions
Throughout this document, certain assumptions are made about nomenclature. The transmission path that outputs the STS-3/STM-1 (AU-4) signal is called the transmit direction, while the transmission path that receives the STS-3/STM-1 (AU-4) signal is referred to as the receive path. The low-speed (LS) side of the device transmits or receives the STS-1/AU-3 signals, while the high-speed (HS) side of the device transmits or receives the STS-3/STM-1 (AU-4) signal. The LSB (least significant bit) of a byte is labeled 0 and the MSB (most significant bit) is labeled N - 1, where N is the total number of bits in the word. A signal that ends in [3--1][7:0] implies there are three separate signals, each containing 8 bits. A control bit that has only one function causes that function to be active when the control bit is set to a logic 1. For example, setting RLSCLKINV, 0x57 to a logic 1 causes the low-speed output clock to be inverted. A control bit with two names performs the first choice when set to a logic 0 and the second choice when set to a logic 1. For example, TSONET_SDH, 0x34 when set to a logic 0 puts the transmit direction in the SONET mode and when set to a logic 1 puts the transmit direction in SDH mode. Where necessary to avoid confusion, numbers may be expressed using a format to specify their base. The following are examples:
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9\D = 9 decimal. 0x04 = 04 hexadecimal. 11\B = 11 binary.
Agere Systems Inc.
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Block Diagram (continued)
SPE OVERHEAD GENERATE
#1R, #2R, #3R
LOCAL CLOCK GENERATION
MICROPROCESSOR INTERFACE
#1T TLSCLKO (19.44 MHz) TLSSPEO, TLSC1J1V1TIMEO, TLSV1TIMEO BUS CONTROL ADD SELECT/ MULTI#2T CAST LOGIC S#1T OVERHEAD MONITOR THSSCLKOT/C (155.52 MHZ), THSSSYNCOT/C (8 kHZ), THSSDATAOT/C (155.52 Mbits/s) LOOPBACK OR SELECT LOGIC THSCLKO (38.88 MHz OR 19.44 MHz), THSSYNCO (8 kHZ), THSDATA[7:0]O (38.88 Mbits/s OR 19.44 Mbits/s), THSPARO (38.88 Mbits/s OR 19.44 Mbits/s)
S#2T
OVERHEAD MONITOR
3:1 MUX LOGIC
TLSDATA[7:0]I
S#3T
OVERHEAD MONITOR TOAC INSERT
TLSPARI #3T
TRANSMIT DIRECTION RECEIVE DIRECTION #1T, #2T, #3T
TTOACCLKO (5.184 MHZ), TTOACSYNCO (8 kHZ), TTOACDATAI (5.184 Mbits/s)
RLSCLKO (19.44 MHz)
#1R TRANSPORT AND PATH MONITORS LOOPBACK SELECT LOGIC TOAC DROP POINTER INTERPRETER
RHSSCLKIT/C (155.52 MHZ) RHSSDATAIT/C (155.52 Mbits/s) OR RHSCLKI (38.88 MHz OR 19.44 MHz), RHSDATA[7:0]I (38.88 Mbits/s OR 19.44 Mbits/s), RHSPARI (38.88 Mbits/s OR 19.44 Mbits/s) BER MONITOR
RLSJ0TIMEO BUS CONTROL DROP #2R SELECT/ MULTICAST LOGIC #3R 1:3 DEMUX LOGIC
RLSDATA[7:0]O
FRAMER
CDR
RLSPARO
RTOACCLKO (5.184 MHZ), RTOACSYNCO (8 kHZ), RTOACDATAO (5.184 Mbits/s)
LOSS OF CLOCK RHSLOSEXTI
LOS
5-5294(F).ar.8
Figure 1. TMUX03155 Block Diagram
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Agere Systems Inc.
Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Pin Information
NC VSS AD4 AD3 AD2 AD1 AD0 A7 A6 A5 A4 A3 VDD A2 A1 A0 RLSPARO RESERVED RLSDATA0O RLSDATA1O RLSDATA2O VSS RLSDATA3O RLSDATA4O RLSDATA5O RLSDATA6O VSS RLSDATA7O VDD RLSCLKO NC VSS RLSJ0TIMEO NC TLSSPEO TLSV1TIME0 TLSCLKO TLSJ0J1V1TIMEO TLSDATA7I TLSDATA6I VDD TLSDATA5I TLSDATA4I TLSDATA3I TLSDATA2I TLSDATA1I TLSDATA0I TLSPARI NC NC VSS VSS 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
VSS VSS AD5 AD6 AD7 NC CS INT WR_DS RD_RW ALE_AS VDD RDY_DTACK MPMUX MPMODE MPMODE3ALE VDD NC NC TCLK VSS TDI TMS TRST TDO VDD SCAN_EN TEST_MODE NC ICT VSS REF5VTOL NC NC NC VDD TTOACCLKO TTOACSYNCO TTOACDATAI VDD RTOACCLKO RTOACSYNCO RTOACDATAO VDD NC NC NC NC RHSLOSEXTI RHSCLKI VSS NC
VSS VSS RHSPARI RHSDATA7I RHSDATA6I RHSDATA5I RHSDATA4I RHSDATA3I RHSDATA2I RHSDATA1I RHSDATA0I NC VDD NC NC NC NC NC NC NC VDD VSS NC NC NC NC VSS VDD NC NC NC VSS VDD NC NC NC NC NC NC NC VDD THSDATA0O THSDATA1O THSDATA2O THSDATA3O THSDATA4O THSDATA5O THSDATA6O THSDATA7O THSPARO VSS NC
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
NC VSS MODE0 MODE1 VDD REF5VTOL THSJ0J1V1I VSS THSCLKI VDD LVDS_REFSEL CTAP_THSSCLKI VDD THSSCLKIT THSSCLKIC CTAP_THSSJ0J1V1I THSSJ0J1V1IT THSSJ0J1V1IC VDD THSSCLKOT THSSCLKOC VSS THSSSYNCOT THSSSYNCOC THSSDATAOT THSSDATAOC VDD LVDS_REF10 LVDS_REF14 LVDS_RESHI LVDS_RESLO VSS RHSSCLKIT RHSSCLKIC CTAP_RHSSCLKI VDD VSS RHSSDATAIT RHSSDATAIC CTAP_RHSSDATAI VDD VSS CDR_TSTMUXO RCDR10K2GND NC RSTN_TST THSCLKO THSSYNCO NC NC RESET VSS
5-4873(F)
Figure 2. Pinout of 208 SQFP Device The pin descriptions for the 208 SQFP package follow in Table 1 on page 10.
Agere Systems Inc.
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Pin Information (continued)
Table 1. Pin Descriptions for the 208-Pin SQFP Package Pin* 143, 142 Symbol THSSCLKIT/C Type Name/Description
Transmit Direction Signals Idiff Transmit High-Speed Serial Clock Input. The transmit clock can LVDS either be 155.52 MHz (serial), 38.88 MHz (nibble), or 19.44 MHz (byte). I Center Tap for Transmit High-Speed Serial Clock Input. The center tap input provides for center-tapped common-mode termination. This input should be terminated through an external capacitor to ground (approximately 0.1 F).
145
CTAP_THSSCLKI
140, 139
THSSJ0J1V1IT/C
Idiff Transmit High-Speed Serial Sync Input. The transmit sync signal LVDS is active during J0 time (8 kHz), J11 time, and V11 time (2 kHz). This signal is active-high and is optional. (See Figure 16 on page 112 for details.) I Center Tap for Transmit High-Speed Serial Sync Input. The center tap input provides for center-tapped common-mode termination. This input should be terminated through an external capacitor to ground (approximately 0.1 F). Transmit High-Speed Clock Input. The transmit clock can either be 38.88 MHz (nibble) or 19.44 MHz (byte). Transmit High-Speed Sync Input. The transmit sync signal is active during J0 time (8 kHz), J11 time, and V11 time (2 kHz). This signal is active-high and is optional. Transmit Low-Speed Output Clock. The STS-1/AU-3 clock will be 19.44 MHz. Transmit Low-Speed Synchronous Payload Envelope (SPE). The STS-1/AU-3 SPE signal is low when the transport overhead is on the input bus (TLSDATA[7:0]I). (See Figure 18 on page 116 for details.) Transmit Low-Speed J0, J1, and V1 Time Signal. J0 time is defined when TLSSPEO is a logic 0, TLSJ0J1V1TIMEO is a logic 1, TLSV1TIMEO is a logic 0, and the J0 byte is on the input bus. J1 time is defined when TLSSPEO is a logic 1, TLSJ0J1V1TIMEO is a logic 1, TLSV1TIMEO is a logic 0, and J11 is on the input bus. (See Figure 18 on page 116 for details.) Transmit Low-Speed V1 Time. This signal is active-high when the current frame contains the V1 byte. V1 time is defined when TLSSPEO is a logic 1, TLSJ0J1V1TIMEO is a logic 1, and TLSV1TIMEO is a logic 1. (See Figure 18 on page 116 for details.) Transmit Low-Speed Data. TLSDATA7I is the most significant bit of the input byte. (See Figure 18 on page 116 for details.)
141
CTAP_THSSJ0J1V1I
148 150
THSCLKI THSJ0J1V1I
Id Id
172 174
TLSCLKO TLSSPEO
O O
171
TLSJ0J1V1TIMEO
O
173
TLSV1TIMEO
O
170, 169, 167--162
TLSDATA[7:0]I
Id
* Pin order follows symbol order, e.g., pin 170 refers to TLSDATA7I. I = input, O = output, I/O = bidirectional signal, Id = input with internal pull-down (~20 kW), Iu = input with internal pull-up (~100 kW), Idiff or Odiff = differential input or output. All I/O not explicitly stated with a buffer type are 5 V compatible. They will tolerate 5 V at their inputs or outputs. LVDS = low-voltage differential signal.
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Agere Systems Inc.
Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Pin Information (continued)
Table 1. Pin Descriptions for the 208-Pin SQFP Package (continued) Pin* 161 Symbol TLSPARI Type Iu Name/Description Transmit Low-Speed Parity Bit. The STS-1/AU-3 parity input is only defined for byte-wide data. The device can be provisioned to receive either odd or even parity.
Transmit Direction Signals (continued)
137, 136
THSSCLKOT/C
Odiff Transmit High-Speed Serial Clock. The STS-3/STM-1 (AU-4) clock LVDS will be 155.52 MHz for serial output data; otherwise, this output is placed in a high-impedance state. Odiff Transmit High-Speed Serial Sync. The STS-3/STM-1 (AU-4) 8 kHz LVDS frame sync is coincident with the first or last bit of the frame. Odiff Transmit High-Speed Serial Data. If the device is operating in the LVDS serial mode, then this output is used as the differential data pin. In nibble or parallel output mode, this output is placed in a highimpedance state. O O O O Transmit High-Speed Clock. The STS-3/STM-1 (AU-4) clock is 38.88 MHz for nibble data, or 19.44 MHz for byte-wide data. Transmit High-Speed Sync. The STS-3/STM-1 (AU-4) 8 kHz frame sync is coincident with the first or last nibble/byte of the frame. Transmit High-Speed Data. Bit 7 is the most significant bit in nibble or byte mode. Transmit High-Speed Parity. The parity output is only defined for nibble or byte-wide data. The device can be provisioned to source either an odd or even parity bit. Transmit TOAC Clock. (5.184 MHz.) Transmit TOAC Sync. (8 kHz.) Transmit TOAC Data. (5.184 Mbits/s.)
134, 133 132,131
THSSSYNCOT/C THSSDATAOT/C
110 109 101--94 102
THSCLKO THSSYNCO THSDATA[7:0]O THSPARO
STS-3/STM-1 (AU-4) Transport Overhead Access Channel (TOAC) Insert 37 38 39 TTOACCLKO TTOACSYNCO TTOACDATAI O O I
d
* Pin order follows symbol order, e.g., pin 170 refers to TLSDATA7I. I = input, O = output, I/O = bidirectional signal, Id = input with internal pull-down (~20 kW), Iu = input with internal pull-up (~100 kW), Idiff or Odiff = differential input or output. All I/O not explicitly stated with a buffer type are 5 V compatible. They will tolerate 5 V at their inputs or outputs. LVDS = low-voltage differential signal.
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Pin Information (continued)
Table 1. Pin Descriptions for the 208-Pin SQFP Package (continued) Pin* 124, 123 122 Symbol RHSSCLKIT/C CTAP_RHSSCLKI Type
diff
Name/Description Receive Direction Signals
Receive High-Speed Serial Clock Input. The STS-3/STM-1 I LVDS (AU-4) serial clock is 155.52 MHz. I Center Tap for Receive High-Speed Serial Clock Input. The center tap input provides for center-tapped common-mode termination. This input should be terminated through an external capacitor to ground (approximately 0.1 F).
119, 118 117
RHSSDATAIT/C CTAP_RHSSDATAI
Idiff Receive High-Speed Serial Data Input. The STS-3/STM-1 (AU-4) LVDS serial data is 155.52 Mbits/s. I Center Tap for Receive High-Speed Serial Data Input. The center tap input provides for center-tapped common-mode termination. This input should be terminated through an external capacitor to ground (approximately 0.1 F). Receive CDR Bias Resistor Input. Must be tied to ground, through an external 10 k 1% resistor. Receive High-Speed Clock Input. The STS-3/STM-1 (AU-4) clock is 38.88 MHz (nibble), or 19.44 MHz for byte-wide data. Receive High-Speed Data Inputs. Data bit 7 is the most significant bit in nibble or byte mode. Receive High-Speed Input Parity. The parity input is only defined for nibble- or byte-wide data. The device can be provisioned to accept either odd or even parity. Receive High-Speed Loss of Signal. This is an active-high signal. Receive STS-1/AU-3 Output Clock. The STS-1/AU-3 clock will be 19.44 MHz for byte-wide data (bus mode). Receive STS1/AU-3 Output J0 Time. This signal will be active (logic 1) each time the J0 byte is output. Receive STS-1/AU-3 Output Data. RLSDATA7O is the most significant bit of the output byte. Receive STS-1/AU-3 Output Parity. The device can be provisioned to source either an odd or even parity bit per byte transfer. Receive TOAC Clock. (5.184 MHz.) Receive TOAC Sync. (8 kHz.) Receive TOAC Data. (5.184 Mbits/s.)
113 50 56--63 55
RCDR10K2GND RHSCLKI RHSDATA[7:0]I RHSPARI
I Id Id Iu
49 179 176 181, 183--186, 188--190 192
RHSLOSEXTI RLSCLKO RLSJ0TIMEO RLSDATA[7:0]O
Id O O O
RLSPARO
O
STS-3/STM-1 (AU-4) Transport Overhead Access Channel (TOAC) Drop 41 42 43 RTOACCLKO RTOACSYNCO RTOACDATAO O O O
* Pin order follows symbol order, e.g., pin 170 refers to TLSDATA7I. I = input, O = output, I/O = bidirectional signal, Id = input with internal pull-down (~20 kW), Iu = input with internal pull-up (~100 kW), Idiff or Odiff = differential input or output. All I/O not explicitly stated with a buffer type are 5 V compatible. They will tolerate 5 V at their inputs or outputs. LVDS = low-voltage differential signal.
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Pin Information (continued)
Table 1. Pin Descriptions for the 208-Pin SQFP Package (continued) Pin* 30 106 Symbol
ICT RESET
Type Iu Iu
Name/Description In-Circuit Test Control (Active-Low). If ICT is forced low, certain output pins are placed in the high-impedance state. Hardware Reset (Active-Low). If RESET is forced low, all internal states in the transceiver paths are reset and data flow through each channel will be interrupted. Test Reset (Active-Low). This pin is for test purposes only; it should be left unconnected. Mode Control. Normal STS-3/STM-1 mode set MODE [1:0] = 10. STS-1 mode set MODE [1:0] = 00 Microprocessor Interface Microprocessor Multiplex Mode. Setting MPMUX = 1 allows the microprocessor interface to accept the multiplexed address and data signals. Setting MPMUX = 0 allows the microprocessor interface to accept demultiplexed (separate) address and data signals. Microprocessor Mode. When MPMODE = 1, the device uses the address latch enable type microprocessor read/write protocol with separate read and write controls. Setting MPMODE = 0 allows the device to use the address strobe type microprocessor read/write protocol with a separate data strobe and a combined read/write control. Microprocessor MODE3 ALE Enable. When the device is in MODE3 (MPMODE = 1 and MPMUX = 0), the ALE signal can be used to retime the address or the address bus can be used directly without being retimed. This is an active-high signal. Write (Active-Low). If MPMODE = 1, this pin is asserted low by the microprocessor to initiate a write cycle. Data Strobe (Active-Low). If MPMODE = 0, this pin becomes the data strobe for the microprocessor. When R/W = 0 (write), a low applied to this pin latches the signal on the data bus into internal registers. Address Latch Enable. If MPMODE = 1, this pin becomes the address latch enable for the microprocessor. When this pin transitions from high to low, the address bus inputs are latched into the internal registers. Address Strobe (Active-Low). If MPMODE = 0, this pin becomes the address strobe for the microprocessor. When this pin transitions from high to low, the address bus inputs are latched into the internal registers. Read (Active-Low). If MPMODE = 1, this pin is asserted low by the microprocessor to initiate a read cycle. Read/Write. If MPMODE = 0, this pin is asserted high by the microprocessor to indicate a read cycle or asserted low to indicate a write cycle.
Mode/In-Circuit Test and Reset Control Inputs
111 153, 154
RSTN_TST
Iu Iu, Id
MODE [1:0]
14
MPMUX
I
15
MPMODE
I
16
MPMODE3ALE
Iu
9
WR_DS
I
11
ALE_AS
I
10
RD_R/W
I
* Pin order follows symbol order, e.g., pin 170 refers to TLSDATA7I. I = input, O = output, I/O = bidirectional signal, Id = input with internal pull-down (~20 kW), Iu = input with internal pull-up (~100 kW), Idiff or Odiff = differential input or output. All I/O not explicitly stated with a buffer type are 5 V compatible. They will tolerate 5 V at their inputs or outputs. LVDS = low-voltage differential signal.
Agere Systems Inc.
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Pin Information (continued)
Table 1. Pin Descriptions for the 208-Pin SQFP Package (continued) Pin* 7 Symbol
CS
Type Iu
Name/Description Chip Select (Active-Low). This pin is asserted low by the microprocessor to enable the microprocessor interface. If MPMUX = 1, an internal 100 k pull-up is on this pin. Interrupt. This pin is asserted high to indicate an interrupt produced by an alarm condition. The activation of this pin can be masked by the microprocessor by setting the appropriate mask bits. Ready. If MPMODE = 1, this pin is asserted high to indicate the device has completed a read or write operation. This pin is in a highimpedance state when CS is high. Data Transfer Acknowledge (Active-Low). If MPMODE = 0, this pin is asserted low to indicate the device has completed a read or write operation. Microprocessor Interface Address/Data Bus. If MPMUX = 0, these pins become the bidirectional, 3-state data bus. If MPMUX = 1, these pins become the multiplexed address/data bus. Microprocessor Interface Address. If MPMUX = 0, these pins become the address bus for the microprocessor interface registers. JTAG Signals JTAG Clock. JTAG Input Data. JTAG Mode Select. JTAG Reset (Active-Low). JTAG Output Data. SCAN Specific Inputs Scan Enable. Place device in scan mode (active-low). Test Mode. Disable all clocks and async resets (active-high). CDR Test Output. Test purpose only. LVDS Control Signals LVDS Reference Select. If LVDS_REFSEL = 0, then use external 1.0 and 1.4 reference voltages. If LVDS_REFSEL = 1, then use internal references. 1.0 V Reference for LVDS Buffers. This signal is optional. 1.4 V Reference for LVDS Buffers. This signal is optional. LVDS Resistor Pins. A 100 1% resistor must be placed between these two pins when using the LVDS buffers.
Microprocessor Interface (continued)
8
INT
O
13
RDY_DTACK
O
5--3, 206--202 201--197, 195--193 20 22 23 24 25 27 28 114 146
AD[7:0]
I/O
A[7:0]
Id
TCLK TDI TMS
TRST
Iu Iu Iu Iu O Iu Id O Iu
TDO
SCAN_EN
TEST_MODE CDR_TSTMUX0 LVDS_REFSEL
129 128 127 126
LVDS_REF10 LVDS_REF14 LVDS_RESHI LVDS_RESLO
I I I I
* Pin order follows symbol order, e.g., pin 170 refers to TLSDATA7I. I = input, O = output, I/O = bidirectional signal, Id = input with internal pull-down (~20 kW), Iu = input with internal pull-up (~100 kW), Idiff or Odiff = differential input or output. All I/O not explicitly stated with a buffer type are 5 V compatible. They will tolerate 5 V at their inputs or outputs. LVDS = low-voltage differential signal.
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Pin Information (continued)
Table 1. Pin Descriptions for the 208-Pin SQFP Package (continued) Pin* 1--2, 21 31, 51, 53--54, 74, 79, 84, 103, 105, 115, 120, 125, 135, 149, 155, 157--158, 177, 182, 187, 207 12, 17, 26, 36, 40, 44, 65, 73, 80, 85, 93, 116, 121, 130, 138, 144, 147, 152, 168, 180, 196 151, 32 Symbol VSS Type I Ground Reference. Name/Description Power and Ground Pins
VDD
I
Power Supply for Digital Circuitry.
REF5VTOL
I
5 V Tolerant Reference Voltage.
* Pin order follows symbol order, e.g., pin 170 refers to TLSDATA7I. I = input, O = output, I/O = bidirectional signal, Id = input with internal pull-down (~20 kW), Iu = input with internal pull-up (~100 kW), Idiff or Odiff = differential input or output. All I/O not explicitly stated with a buffer type are 5 V compatible. They will tolerate 5 V at their inputs or outputs. LVDS = low-voltage differential signal.
Summary of I/O Pins
Table 2. Input/Output Summary Type Input Output Differential Single Ended Differential Single Ended Bidirectional Total Signal No Connect (Reserved) REF5VTOL LVDS_REF10 LVDS_REF14 VDD VSS (GND) Total Package Agere Systems Inc. Number of Pins 8 57 6 35 8 114 45 2 1 1 21 24 208 SQFP 15
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Mode Control Signals (See Register Description on page 54.)
The device is controlled by four control signals: T/RSONET_SDH and T/RSTS3_AU4, 0x34. These signals control the following:
I I I
The type of input signal to expect (low-speed (LS) side--STS-1/AU-3). The expected high-speed (HS) input/output signal format--STS-3/STM-1 (AU-4), or STS-1. The default byte value in the outgoing HS frame.
These provisioning signals are summarized in Table 3 and Table 4. Table 3. Transmit Mode Control Signals TSTS3_AU4 0 = STS-3 1 = AU-4 0 = STS-3 1 = AU-4 TSONET_SDH 0 = SONET1 0 = SONET* 1 = SDH
2
Description Three STS-1 inputs multiplexed to an STS-3 output. Also used for STS-1 mode. See STS-1 Mode section for details. Three AU-3 signals multiplexed to an STM-1 (AU-4) signal. Three STS-1 inputs multiplexed to an STS-3 output. Three AU-3 signals multiplexed to an STM-1 (AU-4) signal.
1 = SDH
1. SONET = OOF 0 1, 4 times detect; default output byte = 0x00. 2. SDH = OOF 0 1, 5 times detect; default output byte = 0xFF.
Table 4. Receive Mode Control RSTS3_AU4 0 = STS-3 1 = AU-4 0 = STS-3 1 = AU-4 RSONET_SDH 0 = SONET1 0 = SONET* 1 = SDH 1 = SDH
2
Description One STS-3 input demultiplexed to three STS-1 outputs. Also used for STS-1 mode. See STS-1 Mode section for details. One STM-1 (AU-4) input demultiplexed to three AU-3 outputs. One STS-3 input demultiplexed to three STS-1 outputs. One STM-1 (AU-4) input demultiplexed to three AU-3 outputs.
1. SONET = OOF 0 1, 4 times detect; default output byte = 0x00; ignore SS bits. 2. SDH = OOF 0 1, 5 times detect; default output byte = 0xFF; verify SS bits = 10.
STS-1 Mode
In STS-1 mode, all other device functions remain the same as in STS-3/STM-1 mode; except, the device runs at one-third the STS-3/STM-1 rate and operates on a single STS-1 frame. The high-speed side operates in the following three modes: 1) as a 51.84 Mbits/s serial interface, 2) as a parallel 12.96 MHz nibble wide, 3) or as a 6.48 MHz byte-wide interface. The low-speed STS-1/AU-3 side operates at 6.48 Mbytes/s and communicates with a single STS-1/AU-3 device (TMPR28051). Since the TOAC interface provides access to the transport overhead in a single STS-1 frame, its clock and data operate at 1.782 MHz, while the sync runs at 8 kHz. For STS-1 mode, set both mode pins 153 and 154 to a logic 0, and set all mode control bits TSTS3_AU4, TSONET_SDH, RSTS3_AU4, RSONET_SDH, 0x34, to a logic 0.
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Agere Systems Inc.
Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Transmit Direction Overview
The following major functions are performed in the transmit direction: STS-1/AU-3 bus mode retiming, input select control, STS-1/AU-3 inputs, out-of-frame (OOF) and loss-of frame (LOF) monitoring, descramble enable/disable, monitor B1 and B2 errors, H4 multiframe and pointer monitor (AU-4 mode only), STS-3 generate, STM-1 (AU-4) frame generation (AU-4 mode), transport overhead access channel (TOAC) insert, STS-3/STM-1 (AU-4) scramble enable, STS-3/STM-1 (AU-4) loopback control, and STS-3/STM-1 (AU-4) output interface.
STS-1/AU-3 Bus Mode Input Retiming
The bus mode provides a single byte-wide bus and parity bit that is shared with up to three devices at 19.44 Mbits/s. The device will source a clock (19.44 MHz), synchronous payload envelope (SPE) indicator, J0J1V1 indicator, and V1 time indicator signals toward the downstream devices. These signals guarantee frame alignment between all three STS-1/AU-3 inputs and H4 byte multiframe values (AU-4 mode). The V1 time signal can be disabled under software control (TLSV1DISABLE, 0x35). The clock can be inverted leaving the device (TLSCLKINV, 0x35). An odd/even parity bit (TLSVOEPAR, 0x35) is verified per byte transfer (TLSPARE[3--1], TLSPARM[3--1], 0x07, 0x10).
Input Select Control
This function determines which signals are multiplexed to form the STS-3 signal. These control bits (TSEL[3-- 1][2:0], 0x3A, 0x38, 0x36) allow loopback (STS-1/AU-3-R to STS-1/AU-3-T), input shuffle, and multicast operations to be possible. The selected STS-1/AU-3 inputs are labeled S#1T, S#2T, and S#3T in Figure 1. Table 5. Input Select Control TSEL [3--1][2:0] 000 (0) 001 (1) 010 (2) 011 (3) 100 (4) 101 (5) 110 (6) 111 (7) Output STS-1/AU-3 #1 Transmit STS-1/AU-3 #2 Transmit STS-1/AU-3 #3 Transmit STS-1/AU-3 #1 Receive (Loopback) STS3 Mode Only STS-1/AU-3 #2 Receive (Loopback) STS3 Mode Only STS-1/AU-3 #3 Receive (Loopback) STS3 Mode Only STS-1/AU-3 #1 Transmit STS-1/AU-3 #1 Transmit
STS-1/AU-3 Inputs
The SONET/SDH STS-1/AU-3 frame is comprised of 9 rows x 90 columns that repeat at an 8 kHz rate. Each column is 1-byte wide. The frame contains three columns of transport overhead, one column of path overhead, and 86 columns of payload. For column byte definitions, see Table 6 on page 18.
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Transmit Direction Overview (continued)
STS-1/AU-3 Inputs (continued)
The 27 bytes of transport overhead from each STS-1/AU-3 input must be aligned* (A1-1, A1-2, A1-3 must all be coincident from all three STS-1/AU-3 inputs) and are allocated as shown in Table 6. Table 6. Expected STS-1/AU-3 Input Frame Format Transport Overhead Col. 1 Row 1 Row 2 Row 3 Row 4 Row 5 Row 6 Row 7 Row 8 Row 9 A1

Payload Col. 4 J1 B3 C2 G1 F2 H4
Col. 2 A2
Col. 3 J0 F1 D3 H3 K2 D6 D9 D12 E2
Col. 5--90 X X X X X X X X X
B1
E1 D2 H2
D1 H1 B2

K1 D5 D8 D11 M0
D4 D7 D10 S1
Z3 Z4 Z5
Monitored in STS-1 mode. Monitored in AU-4 mode.
Note: X = don't care (payload). The path overhead (POH) can start anywhere within the SPE and cannot be accessed in the STS-3 mode. In the AU-4 mode, the pointer is fixed at 522\D; therefore, the J1 byte will always be in row 1, column 4. The H4 byte is the only valid byte in the POH and all other bytes are ignored.
Out-of-Frame (OOF) and Loss-of-Frame (LOF) Monitoring
The device monitors for out-of-frame (OOF) and loss-of-frame (LOF) states on each selected STS-1/AU-3 input (TLSOOF[3--1], TLSOOFD[3--1], TLSOOFM[3--1], TLSLOF[3--1], TLSLOFD[3--1, TLSLOFM[3--1], 0x08, 0x11, 0x19). Each input will be considered out-of-frame until two successive framing patterns (0xF628) separated in time by 125 s occur without framing byte errors. Each selected STS-1/AU-3 input will be considered in frame until five (SDH)/four (SONET) successive frames separated in time by 125 s occur with errored framing patterns. The device will be considered in the LOF state when an OOF condition persists for 24 consecutive frames (3 ms) or clear when the OOF condition is inactive for 24 consecutive frames (3 ms) with the correct framing patterns spaced 125 s apart.
Descramble Enable/Disable
Each selected STS-1/AU-3 input can be descrambled (TLSDSCR[3--1], 0x3A, 0x38, 0x36) according to the frame synchronous descrambling sequence 1 + x6 + x7. The sequence is reset to 1111111 at the beginning of the byte following the C1 byte and descrambles all of the STS-1/AU-3 data except the A1, A2, and J0 bytes. Writing a logic 1 to the appropriate bit causes the selected STS-1/AU-3 signal to be descrambled.
* Can be provided by the Agere TMPR28051 mapper device.
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Transmit Direction Overview (continued)
Monitor B1 and B2 Errors
The device verifies B1 and B2 bit interleaved parity (BIP) values on each selected STS-1/AU-3 input. The device will count BIP errors or block errors under software control (BITBLOCKCNT, TLSB1ECNT[3--1][15:0], TLSB2ECNT[3--2][15:0], TLSB2ECNT1[17:0], 0x34, Page 1 - 0x80--0x85, Page 1 - 0x86--0x88, Page 1 - 0x89--0x8C). These counters will update on LATCH_CNT, 0x04 and are large enough to store at least 1 second's worth of data.
H4 Multiframe and Pointer Monitor (AU-4 Mode Only)
In this mode, all three input signals are required to have pointer values (H1, H2) with the same fixed value of 522\D. This ensures the J1 byte starts in row 1, column 4. The H4[1:0] multiframe bits must be the same from all inputs and equal to the internally expected value. This is required because the output STM-1 (AU-4) signal only has one H4 byte. The device will synchronize its H4 internal expected value to a 1 after detecting an embedded 2 kHz sync in the local frame sync signal (THS(S)J0J1V1I(T/C)). The device will declare a pointer match after two consecutive pointer values of 522\D are detected 125 s apart. A pointer mismatch will be declared after five successive frames separated in time by 125 s occur with errored pointer values (TLSPTRMIS[3--1], TLSPTRMISD[3--1], TLSPTRMISM[3--1], 0x1A, 0x09, 0x12). The device will declare an H4 multiframe match after two consecutive H4 values match the expected value spaced 125 s apart. An H4 multiframe mismatch will be declared after five successive frames separated in time by 125 s occur with H4 values not equal to the expected value (TLSH4MIS[3--1], TLSH4MISD[3--1], TLSH4MISM[3--1], 0x1A, 0x09, 0x12).
Agere Systems Inc.
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Transmit Direction Overview (continued)
STS-3 Generate
The device will create the overhead according to Table 7. The POH byte locations are not fixed and cannot be accessed. Table 7. STS-3 Output Overhead Format STS-3 Overhead Col. 1 Row 1 Row 2 Row 3 Row 4 Row 5 Row 6 Row 7 Row 8 Row 9 A1-1 B1 D1* H1-1 B2-1 D4* D7* D10* S1* Col. 2 A1-2 B1-2* D1-2* H1-2 B2-2 D4-2* D7-2* D10-2* Z1-2* Col. 3 A1-3 B1-3* D1-3* H1-3 B2-3 D4-3* D7-3* D10-3* Z1-3* Col. 4 A2-1 E1* D2* H2-1 K1 D5* D8* D11* Z2-1* Col. 5 A2-2 E1-2* D2-2* H2-2 K1-2* D5-2* D8-2* D11-2* Z2-2* Col. 6 A2-3 E1-3* D2-3* H2-3 K1-3* D5-3* D8-3* D11-3* M1 Col. 7 J0 F1* D3* H3-1 K2 D6* D9* D12* E2* Col. 8 Z0-2 F1-2* D3-2* H3-2 K2-2* D6-2* D9-2* D12-2* E2-2* Col. 9 Z0-3 F1-3* D3-3* H3-3 K2-3* D6-3* D9-3* D12-3* E2-3* Col. 10--270 Payload
* Access through transmit TOAC (see Table 17 on page 37).
Note: Bold type within the table is not defined in the standard and is labeled here for clarity. The following values are assigned to the transmitted overhead bytes: A1--11110110 (0xF6) A2--00101000 (0x28) J0--TJ0DINS[7:0], 0x3F Z0-2--TZ02DINS[7:0], 0x40 Z0-3--TZ03DINS[7:0], 0x41 B1--Variable value (BIP-8 parity) F1--Variable value TF1DINS[7:0], 0x42 H1-1, 2, 3--Passed through from respective STS-1 H2-1, 2, 3--Passed through from respective STS-1 H3-1, 2, 3--Passed through from respective STS-1 B2-1, 2, 3--Variable value (BIP-24) K1--Variable value TAPSINS[12:5], 0x43, 0x44 K2--Variable value TAPSINS[4:0], TK2INS[2:0], 0x43, 0x44--RDI-L, AIS-L S1--Variable value TS1DINS[7:0], 0x45 M1--Variable value (Section FEBE--Number of B2 Errors) TSFEBEINH, 0x3E All bytes not specified above, either: (1) Are set to the fixed stuff value (0x00 (SONET)). (2) Are TOAC value-inserted. (3) Have passed through from the selected STS-1 input, all under software control. The variable values are described beginning on page 30 in the Maintenance Functions section of this document.
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Transmit Direction Overview (continued)
STM-1 (AU-4) Frame Generation (AU-4 Mode)
The device will create the overhead according to the following table. The path overhead bytes are created in this mode. The three AU-3 inputs are converted to TUG-3 format and inserted into a VC-4 that is multiplexed into an AU-4. Table 8. STM-1 (AU-4) Output Overhead Format
STM-1 (AU-4) Overhead Col. 1 Col. 2 Col. 3 Col. 4 Col. 5 Col. 6
Row 1 Row 2 Row 3 Row 4 Row 5 Row 6 Row 7 Row 8 Row 9 A1-1 B1 D1* H1-1 B2-1 D4* D7* D10* S1* A1-2 B1-2* D1-2* Y B2-2 D4-2* D7-2* D10-2* Z1-2* A1-3 B1-3* D1-3* Y B2-3 D4-3* D7-3* D10-3* Z1-3* A2-1 E1* D2* H2-1 K1 D5* D8* D11* Z2-1* A2-2 E1-2* D2-2* 1* K1-2* D5-2* D8-2* D11-2* Z2-2* A2-3 E1-3* D2-3* 1* K1-3* D5-3* D8-3* D11-3* M1
AU-4 Payload Col. 7 Col. 8 Col. 9 POH
10 J1 B3 C2 G1 F2 H4 Z3 Z4 Z5 F I X E D S T U F F F I X E D S T U F F N P I S T U F F N P I S T U F F N P I S T U F F F I X E D S T U F F F I X E D S T U F F F I X E D S T U F F T U G 3 A T U G 3 B T U G 3 C J0 F1* D3* H3-1 K2 D6* D9* D12* E2* Z0-2 F1-2* D3-2* H3-2 K2-2* D6-2* D9-2* D12-2* E2-2* Z0-3 F1-3* D3-3* H3-3 K2-3* D6-3* D9-3* D12-3* E2-3*
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
22-- 270
-- -- -- -- -- -- -- -- --
* Access through transmit TOAC (see Table 17 on page 37).
Note: Bold type within the table is not defined in the standard and is labeled here for clarity. The following values are assigned to the transmitted overhead bytes: A1--11110110 (0xF6) A2--00101000 (0x28) J0--Variable value TJ0DINS[7:0], 0x3F Z0-2--Variable value TZ02DINS[7:0], 0x40 Z0-3--Variable value TZ03DINS[7:0], 0x41 B1--Variable value (BIP-8 Parity) F1--Variable value TF1DINS[7:0], 0x42 H1-1--01101010 H2-1--00001010 (pointer value of 522\D) Y--10011011 (NDF, SS, PTR)--Concatenation indication 1 --All ones pattern H3-1, 2, 3--Default byte value (0xFF) B2-1, 2, 3--Variable value BIP-24 K1--Variable value TAPSINS[12:5], 0x43, 0x44 K2--Variable value TAPSINS[4:0], TK2INS[2:0], 0x43, 0x44--RDI-L, AIS-L S1--Variable value TS1DINS[7:0], 0x45 M1--Variable value (section FEBE--number of B2 errors) TSFEBEINH, 0x3E
Access through transmit TOAC.
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Transmit Direction Overview (continued)
STM-1 (AU-4) Frame Generation (AU-4 Mode) (continued)
Path Bytes J1--64-byte programmable sequence TJ1INS, 0x3E, TJ1DINS[64--1][7:0], 0x3E, 0x80--0xBF B3--Variable value BIP-8 C2--TC2DINS[7:0], 0x46 G1[7:4]--REICNT (B3 errors from receive side) TPFEBEEINS, 0x4D G1[3]--RDI indication TPRDIINS, 0x4B G1[2:0]--Default value F2--Variable value TF2DINS[7:0], 0x47 H4[1:0]--Position indicator (multiframe value (00\B to 11\B)) Z3--Variable value TZ3DINS[7:0], 0x48 Z4--Default value Z5--Variable value TZ5DINS[7:0], 0x49 Fixed stuff = depends on TSONET_SDH, 0x34 value (SONET = 0x00, SDH = 0xFF) NPI (null pointer indicator--byte 1, byte 2, and byte 3) = (10011011, 11100000, 11111111). NPI is generated for compatibility with older devices. All bytes not specified above, either: (1) Are set to the fixed stuff value 0xFF (SDH). (2) Are TOAC value inserted. (3) Have passed through from the selected AU-3 input, all under user control.
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Transmit Direction Overview (continued)
Transport Overhead Access Channel (TOAC) Insert
The device will allow the insertion of overhead data from the transmit TOAC under user control. (See TTOAC in the Maintenance Functions section, page 36, for more details.)
STS-3/STM-1 (AU-4) Scramble Enable
Scrambling of the STS-3/ STM-1 (AU-4) signal is provisionable (THSSCR, 0x3D). A frame synchronous scrambling sequence 1 + x6 + x7 is used. The sequence is reset to 1111111 at the beginning of the byte following the Z03 byte and scrambles all of the STS-3/STM-1 (AU-4) data except all the A1, A2 and J0, Z0 bytes. Writing a logic 1 to this bit causes the signal to be scrambled.
STS-3/STM-1 (AU-4) B1, B2, and B3 BIP Generation
The device will generate a B1-BIP-8, B2-BIP-24, and a B3-BIP-8 (AU-4 mode only) on the output signal. Each BIP calculator can be programmed to insert an inverted BIP value (THSB1ERRINS, THSB2ERRINS[3--1], THSB3ERRINS, 0x4C).
STS-3/STM-1 (AU-4) Loopback Control
The output STS-3/STM-1 (AU-4) signal can be replaced by the receive STS-3/STM-1 (AU-4) signal under software control (RHS2THSLB, 0x3D). The output format (bit, nibble, or byte) will be the same as the receive input format not the transmit output port format. Note: The transmit port type must be programmed to be the same as the receive input type.
STS-3/STM-1 (AU-4) Output Interface
The transmit STS-3/STM-1 (AU-4) output can either be serial at 155.52 Mbits/s, nibble at 38.88 Mbits/s, or byte at 19.44 Mbits/s. This is controlled by writing to THSPTYPE[1:0], 0x3C. The data is clocked out of the device on the rising edge of the clock. This clock can be inverted leaving the device (THSCLKINV, 0x3C). When provisioned in the parallel or nibble mode, an even or odd parity bit is generated per transfer (THSPAROEG, 0x3C). The output sync can be programmed to be active on the first clock cycle of the frame (A1-1 coincident with sync) or the last clock cycle of the frame (THSSA1orEND, 0x3C). The output clock, sync, and data signals can be placed in a high-impedance state under user control (THSCHIZ = 1, THSSHIZ = 1, THSDHIZ = 1, 0x3D). Unused outputs in serial and nibble mode will be placed in a highimpedance state automatically by the device.
Receive Direction Overview
The following functions are performed in the receive direction: input retime, clock and data recovery, STS-3/STM-1 (AU-4) framing, loss-of-signal detection, loopback select logic, RSTS-3/STM-1 (AU-4) frame synchronous descrambling, TOAC drop, B1, B2, and B3 checking, monitoring functions, pointer interpretation, data demultiplex and conversion (AU-4 mode only), STS-1/AU-3 output byte control, B1 and B2 generate, STS-1/AU-3 output scramble, output selection logic, and output data formatter.
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Receive Direction Overview (continued)
Input Retime
The device accepts either a serial 155.52 MHz-Mbits/s, nibble 38.88 MHz-Mbits/s, or byte parallel 19.44 MHzMbits/s clock-data STS-3/STM-1 (AU-4) input. This is controlled by writing to RHSPTYPE[1:0], 0x55. The user can configure which edge of the clock to use to retime the data. RHSEDGE, 0x55 = 1 uses the rising edge; RHSEDGE = 0 uses the falling edge. If in nibble or parallel mode, an odd/even parity bit (RHSVOEPAR, 0x55) is verified per transfer (RHSPARE, RHSPARM, 0x0A, 0x13), otherwise, this indicator is disabled.
Clock and Data Recovery
The device provides an optional clock and data recovery circuit (CDR) on the serial STS-3/STM-1(AU-4) input. The CDR aligns the STS-3/STM-1 data signal to a local clock and then outputs a retimed data and clock signal. The input data and local clock rates need not be synchronous. The CDR only works at the nominal 155 Mbits/s rate and uses the high-speed transmit input clock (THSSCLKIT/C) as a reference for the local clock. The CDR is enabled by the RHSPORCDRSEL bit, 0x57.
STS-3/STM-1 (AU-4) Framing
The device will frame on the input STS-3/STM-1 (AU-4) signal. The state of the framer (RHSOOF), as well as any changes to this state (RHSOOFD, RHSOOFM, 0x0A, 0x13), will be reported. A loss-of-frame (RHSLOF, 0x1B) state bit, as well as any changes to this state (RHSLOFD, RHSLOFM, 0x0A, 0x13), will be reported. Framing Algorithm The 32-bit (A1-2, A1-3, A2-1, A2-2) framing pattern will be used in the frame detection. The device will be considered out of frame until two successive framing patterns separated in time by 125 s occur without framing byte errors. The device will be considered in frame until five (SDH)/four (SONET) successive frames separated in time by 125 s occur with errored framing patterns. If the framer transitions to the out-of-frame state, the framer will remain synchronized to the last known frame boundary or the latest detected unerrored framing pattern. The device will be considered in the loss-of-frame state (LOF) when an OOF condition persists for 24 consecutive frames (3 ms). The device will transition out of the LOF state after receiving 24 consecutive frames with the correct framing patterns spaced 125 s apart and the OOF condition is clear.
Loss of Signal
The device will detect a loss-of-signal condition by monitoring a unique input signal pin (RHSLOSEXTI) or detecting a continuous all-zeros/all-ones pattern for 51.44 ns to 105 s in 51.44 ns steps (LOSDETCNT[10:0], 0x58-- 0x59) before data is descrambled. To recover from the LOS state receiving two consecutive frames with the correct framing pattern spaced 125 s apart without an incoming LOS all-zeros/ones pattern will cause an LOS state to be cleared. This recovery applies to both internal and external LOS failure causes. The device will report this condition to the microprocessor interface (RHSLOS, RHSLOSD, RHSLOSM, 0x1B, 0x0A, 0x13).
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Receive Direction Overview (continued)
Loopback Select Logic
The device can be configured to loopback the transmit STS-3/STM-1 (AU-4) (THS2RHSLB = 1, 0x55) or accept the local STS-3/STM-1 (AU-4) signal (THS2RHSLB = 0). While in the loopback mode, the RHSOOF, RHSLOF, and RHSLOS (0x1B) state bits are inhibited from causing an alarm indication signal (AIS) from being generated on the STS1/AU-3 output signals.
RSTS-3/STM-1 (AU-4) Frame Synchronous Descrambling (SONET/SDH)
The device will descramble the received SONET/SDH data (minus the first row of SOH) according to the frame synchronous descrambling polynomial; specifically: f(x) = 1 + x6 + x7. Under software control, frame descrambling can be disabled (RHSDSCR = 1, 0x55).
TOAC Drop
This channel drops all of the transport overhead bytes from the STS-3/STM-1 (AU-4) signal. (See RTOAC in the Maintenance Functions section, page 44, for more details (RTOACCLKO, RTOACSYNCO, RTOACDATAO)).
B1, B2, and B3 Checking
The device will monitor the incoming B1, B2, and B3 values for errors. The error counts will be latched when the LATCH_CNT signal transitions from a low to a high (RHSB1ECNT[15:0], RHSB2ECNT[17:0], RHSB3ECNT[3--1][15:0], Page 1 - 0x8D--0x8E, Page 1 - 0x8F--0x91, Page 1 - 0x92--0x97). These counters will either count bit or block errors (BITBLOCKCNT, 0x34).
Monitoring Functions
The following transport overhead and path overhead bytes are monitored for failures or changes in states ((J0, Z0-2, Z0-3, F1, K1K2 (APS bytes), S1, M1), (J1,C2, G1, F2, H4, Z3, Z5)). The bit error rate of the incoming STS-3/ STM-1 (AU-4) signal is calculated to create signal fail and signal degrade indicators. (See Maintenance Functions Disabled During Failure Conditions in the Maintenance Functions section, page 28, for more details.)
Pointer Interpretation
The device will evaluate the current pointer state for the normal state, Path AIS (PAIS) state, or loss-of-pointer (LOP) conditions, as well as pointer increments and decrements (that are counted in RPTR_INC[3--1][10:0] and RPTR_DEC[3--1][10:0] counters (0x98--0xA3), respectively). The current pointer state (RLOP[3--1], RPAIS[3--1], 0x1C) and any changes in pointer condition (RLOPD[3--1], RLOPM[3--1], RPAISD[3--1], RPAISM[3--1], 0x0B, 0x14), are reported to the control system. When the device is receiving a concatenated signal (STM-1(AU-3)), the RCONCATMODE, 0x55 bit must be set for the concatenation state machines (CONCAT_STATE[3--2][1:0], 0x1C, 0x1D) on ports 2 and 3 to contribute to pointer evaluation. This state machine implements the pointer interpretation algorithm described in ETS 300 417-1-1: January 1996 Annex B. The number of consecutive conditions for invalid pointer and invalid concatenation indication are programmable with a range 8--10 (CNTCIP_ICI[1:0], 0x5F).
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Receive Direction Overview (continued)
Data Demultiplex and Conversion (AU-4 Mode Only)
The device will demultiplex the STS-3/STM-1 (AU-4) signal into three STS-1/AU-3 signals, respectively. In the AU-4 mode, a conversion between the AU-4 payload format and the AU-3 payload format is performed. This requires the location of the J1 byte to be known, while this is not the case in the STS-3 mode, where the highspeed signal is byte demultiplexed and no format conversion occurs.
STS-1/AU-3 Output Byte Control
The output overhead bytes are controlled in one of four ways: 1. Errors can be inserted. 2. Values from the high-speed STS-3/STM-1 signal can be copied or set to the byte default. 3. Values can be inserted under software control. 4. Values can be inserted under hardware control. Table 9 specifies the specific control allowed for each overhead byte. Table 18 in the Maintenance Functions section provides details for selecting each control mode. Table 9. STS-1/AU-3 Format and Overhead Control Summary Transport Overhead Col. 1 Row 1 Row 2 Row 3 Row 4 Row 5 Row 6 Row 7 Row 8 Row 9 A1 B1 D1 H1 B2
1 2
Payload Col. 3 J03 F1
2, 3 2 4
Col. 2 A21 E1 H2
2 2
Col. 4 J14 B3 C2 F2 Z3 Z5
4 4
Col. 5--90 X X X X X X X X X
D2 K1
D3 H3 K2 D6 D9 E2
1, 4 1 2 2 2
1, 4
G1 H4
1, 3 2 2 2
1, 3 2 2 2
4 4
D4 D7 S1
D5 D8 M0
4
D10
D11
D12
Z4
4
2
1, 5
2
1.Error insert. 2.Input pass or default value. 3.Software overwrite. 4.Copy of the selected byte from the incoming STM-1 (AU-4) frame; otherwise, the bytes pass without being changed (POH can start anywhere within the SPE). 5.Hardware overwrite.
Note: X = don't care (payload).
B1 and B2 Generate
The B1 and B2 values of the outgoing STS-1/AU-3 signal are calculated. An error can be inserted into the B1 and B2 values on a per STS-1/AU-3 basis (RB1ERRINS[3--1], RB2ERRINS[3--1], 0x63).
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Receive Direction Overview (continued)
STS-1/AU-3 Output Scramble
The device allows scrambling of the output signals on a per-output basis (RLSSCR[3--1], 0x57).
Output Selection Logic
The demultiplexed signals can be routed to any output port or can be multicast to more than one port. The control bits (RSEL[3--1][1:0], 0x56) allow this to occur under software control. See Table 10. Table 10. STS-1/AU-3 Output Select Control RSEL [3--1][1:0] 00 (0) 01 (1) 10 (2) 11 (3) Output STS-1/AU-3 #1 Receive STS-1/AU-3 #2 Receive STS-1/AU-3 #3 Receive Undefined
Output Data Formatter
The device outputs one clock at 19.44 MHz, one J0 time signal, an 8-bit data bus, and an odd/even (RPLSPAROEG, 0x57) parity bit. The bus can be shared with up to three other devices. Each device determines its time slot using the J0 time signal. The byte coincident with the J0 time sync signal is always available for device number 1. Subsequent bytes are available for device 2, device 3, and then device 1 again. The sense of the 19.44 MHz output clock can be inverted under user control (RLSCLKINV, 0x57).
Maintenance Functions
Maintenance functions are associated with monitoring signals and conditions in the device. This section is divided into a common section, a transmit section, and a receive section.
Agere Systems Inc.
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Maintenance Functions (continued)
Maintenance Functions Disabled During Failure Conditions
Several maintenance functions are disabled during failure conditions. These are listed in the following table. Event and status information will be disabled and all BIP and far-end bit error (FEBE) counters will be held at 0. Table 11. Monitors Disabled During Failure Conditions Direction Transmit TILOC (0x19) TLSOOF[3--1] and TLSOOF_AISINH[3--1] or TLSLOF[3--1] and TLSLOF_AISINH[3--1] (0x19, 0x37, 0x39, 0x3B) RHSLOS or RHSLOF or RHSOOF (0x1B) Receive RILOC and RRILOC_AISINH (0x1B, 0x58) RHSLOS and RRHSLOS_AISINH or RHSLOF and RRHSLOF_AISINH or RHSOOF and RRHSOOF_AISINH (0x1B, 0x58) Failure Monitors Disabled Transmission path and all monitors disabled TLSB1ECNT[3--1][15:0], TLSB2ECNT[1][17:0], TLSB2ECNT[3--2][15:0] (Page 1 - 0x80--0x8C)
SFEBE and PFEBE (AU-4 mode only) insert (value set to 0) Transmission path and all monitors disabled J0Z0MON, F1MON, APSMON, K2MON, LRDIMON, LAISMON, RHSSF, RHSSD, RHSB1ECNT[15:0], RHSB2ECNT[16:0], RSFEBECNT[7:0], RPFEBECNT[3--1][15:0], and all path monitoring functions (0x1B, 0xA6--0xAC, 0x8E) All path monitoring functions: J1, C2, B3, G1, F2, H4, Z3, Z5
(RPAIS[3:1] or RLOP[3:1]) and PAISLOP_AISINH (0x1C, 0x57)
Common Maintenance and Control Functions
The common section addresses maintenance functions that are common to both directions. Device Reset The device will provide a device reset function (RSTCTL, 0x04). This device reset will be initiated by a unique input signal or by a command received through the control interface. A device reset will set all maintenance and control registers to their default values. A device reset is service affecting. Note: This signal must toggle from 0 1 0. Composite Service Request The device will provide a summary of the device monitoring conditions (INT, 0x00). Mask Bit Operation Mask bits will only inhibit the contribution of the event or delta bit contributing to the interrupt. The event or delta bits will not be cleared if the corresponding mask bit is cleared. Delta and event bits clear-on-read. 28 Agere Systems Inc.
Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Maintenance Functions (continued)
Common Maintenance and Control Functions (continued)
Device Version and Device ID Number The device will have a version number (DEVVER[7:0], 0x03). The version increments each time the device functionality is changed, from the controller's perspective. The device ID (DEVID[15:0], 0x01--0x02) is a fixed pattern used to identify the device by software. Scratch Byte The device will provide a 1-byte scratch register for the control interface to verify write capability to the device (SCRATCH[7:0], 0x06). Multibyte Registers If a read value parameter register requires more than 8 bits, the device must prevent the value from changing between 8-bit read commands. In these cases, the controller reads the lowest address byte first and transfers the higher address bytes to a holding register where the value is held until the controller reads them. Similarly, if a multibyte writable register is implemented, the controller writes the lowest address byte first, which is stored in a holding register until the controller writes the highest address byte, and then all of the bytes take effect. To simplify device design, the controller reads or writes all of the bytes of a multibyte register before reading or writing other registers so that the holding registers may be shared among all multibyte registers. This read/write operation is valid on all multibyte registers not controlled by the LATCH_CNT, 0x04 bit. Update Counter Control For performance monitoring purposes, there are a number of BIP, FEBE, and pointer interpreter increment/decrement error counters in the receive/transmit section. All of these internal counters are comprised of a running error counter and a hold register that present stable results to the microprocessor. The counts in all of the running counters are latched to the hold registers when LATCH_CNT, 0x04 is written from a logic 0 to a logic 1. This zeros all of the running counters. The results are held to be read by the microprocessor. All of the internal counters have the ability to store more than 1 second's worth of counts, so as long as the LATCH_CNT occurs every second, or faster, no counts will be lost. In case this doesn't happen, all of the running counters will hold their maximum value rather than roll over to 0. The following counters1 are affected by LATCH_CNT:
I I I I I I I I I I
TLSB1ECNT[3--1][15:0], 0x08--0x85 TLSB2ECNT[1][17:0], 0x86--0x88 TLSB2ECNT[3--2][15:0], 0x89--0x8C RHSB1ECNT[15:0], 0x8D--0x8E RHSB2ECNT[17:0], 0x8F--0x91 RHSB3ECNT[3--1][15:0], 0x92--0x97 RPTR_INC[3--1[10:0], 0x98--0x9D RPTR_DEC[3--1][10:0], 0x9E--0xA3 RSFEBECNT[17:0], 0xA4--0xA6 RPFEBECNT[3--1][15:0], 0xA7--0xAC
1 All addresses for these counters are in Page 1 registers.
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Maintenance Functions (continued)
Common Maintenance and Control Functions (continued)
Bit or Block Count The device allows all counters, except the pseudorandom error counter, to either count the actual number of bit errors or the number of blocks (a block equals one frame) that contain an error (BITBLOCKCNT, 0x34). The section and path FEBE counters count the actual number of bit errors or the number of blocks that contain an error (FEBEBITBLOCKCNT, 0x34).
Transmit Functions
The transmit section addresses maintenance functions that are unique to the transmit direction. Parity (B1, B2, B3) The device will perform a bit interleaved BIP-8 parity (B1) calculation and will write these bits into the B1 section overhead byte. The device will perform a bit interleaved BIP-24 parity (B2) calculation and will write these bits into the B2 line overhead byte. The device will perform a bit interleaved BIP-8 parity (B3) calculation and will write these bits into the B3 path overhead byte (AU-4 mode only). The device can perform a B1 (THSB1ERRINS, 0x4C), B2 (THSB2ERRINS[3--1], 0x4C), and B3 (THSB3ERRINS, 0x4C) parity byte inversion via microprocessor control. A1, A2 Error Enable The device will allow, under software control, from 1 to 32 continuous frames to have errored A1A2 patterns in the outgoing frame (TA1A2ERRINS[4:0], 0x4D and TA1A2ERREN, 0x04). Section Trace/Growth Byte Insert (J0/Z0) The device inserts the data written into TJ0DINS[7:0], 0x3F, TZ02DINS[7:0], 0x40, and TZ03DINS[7:0], 0x41 into the outgoing J0/Z0 bytes. Fault Location Insert (F1) Via microprocessor control of TF1INS, 0x3E and TF1DINS[7:0], 0x42, data information may be inserted into the outgoing F1 byte. Direct microprocessor insert has higher priority than the TOAC insert control bit (TTOAC_F1[1:0], 0x51). Sync Status Byte Insert (S1) Via microprocessor control of TS1INS, 0x3E and TS1DINS[7:0]0x45, data information may be inserted into the outgoing S1 byte. Direct microprocessor insert has higher priority than the TOAC insert control bit (TTOAC_Z1[1:0], 0x51). Automatic Protection Switch (APS) Insertion (K1[7:0], K2[7:3]) The device writes the K1 and K2 bytes into the transmit K1 and K2 overhead bytes (TAPSINS[12:0], 0x43, 0x44). The K1 and K2[7:3] bits will only change when both values are valid. The TAPSINS[4:0], 0x44 byte is the trigger for updating the APS bytes in the outgoing frame.
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Maintenance Functions (continued)
Transmit Functions (continued)
APS Babbling Test Control Setting the TAPSBABLEINS, 0x4D register, via microprocessor control, forces the APS bytes (K1[7:0], K2[7:3]) to an inconsistent state. Line Remote Defect Indication (RDI-L) Insertion (K2[2:0] = 110) The device will write Line RDI into the data signal using the following equation: TLRDIINT =(RILOC AND TRILOC_LRDIINH) OR (RHSLOS AND TRHSLOS_LRDIINH) OR (RHSOOF AND TRHSOOF_LRDIINH) OR (RHSLOF AND TRHSLOF_LRDIINH) OR (RLAISMON AND TRLAISMON_LRDIINH) OR (RHSSF AND TRHSSF_LRDIINH); (See 0x1A, 0x1B, 0x1D, and 0x4A.) Hardware insert of Line RDI will occur when TLRDIINT, 0x1A is active and the software insert control bit (TLRDIINH, 0x4A) is disabled. User-provided data (TK2INS[2:0], 0x43) will be inserted into the K2[2:0] bits in the STS-3/STM-1 (AU-4) frame when TLRDIINH = 0. The insertion of Line RDI consists of writing the pattern 110 into the three LSBs of the K2 LOH byte. Unequipped and AIS Generation (Automatic/Manual) Line AIS or AU4-AIS or TUG-3 AIS can be generated automatically by the hardware under certain failure conditions or via microprocessor control only. This is accomplished with the following equations and control signals: FAILURE[3--1] = ((TLSOOF[3--1] AND TLSOOF_AISINH[3--1]) OR (TLSLOF[3--1] AND TLSLOF_AISINH[3--1]))
H4PTRMIS[3--1] = ((TLSH4MIS[3--1] AND TLSH4MIS_AISINH[3--1]) OR (TLSPTRMIS[3--1] AND (TLSPTRMIS_AISINH[3--1])) AND STS1_AU4; AU-4 mode only LAIS[3--1] = AU4AISGen = TLS_LAISINS[3--1] OR FAILURE[3--1] OR H4PTRMIS[3--1]; LAIS1 AND LAIS2 AND LAIS3;
(See 0x1A, 0x37, 0x39, 0x3B.) Each alarm contribution that can cause AIS generation can be selectively inhibited. Line AIS is generated in the STS-3 mode per STS-1 input when the appropriate FAILURE[3--1] or TLS_LAISINS[3--1] (software enable) signals are active. (Line overhead and the entire payload is set to an all-ones pattern.) In this mode, the H4PTRMIS[3--1] contribution will always be 0. AU4-AIS generation will set all H1, H2, H3, and payload bytes to an all-ones pattern in the output STM-1 (AU-4) signal. TUG-3 AIS generation will force all the data in the selected TUG-3 signal to be set to an all-ones pattern. In the STS-3 mode, an unequipped signal can be generated for any STS1 input under software control (TLS_UNEQUIP[3--1], 0x3B, 0x39, 0x37 and (H1 = 0110SS00 AND H2 = 00000000)) and the selected payload is set to 0). In AU-4 mode, the H1 and H2 bytes will not change from their default values and the entire payload will be set to 0. The SS bits will be set to the value written into register bits (TSS[1:0], 0x3E). AIS generation has higher priority than unequipped signal generation.
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Maintenance Functions (continued)
Transmit Functions (continued)
H1 and H2 Corruption Setting the TH1H2CRUPEN[3--1], 0x4E, register, via microprocessor control, allows the outgoing H1 and H2 values to be corrupted for each STS-1 channel. Either an invalid pointer or a continuous new data flag can be inserted (TH1H2CRUPPorNDF, 0x4E). Loss-of-Transmit Clock or Loss-of-Frame Sync The device will detect a loss-of-transmit clock condition for the clock input in the transmit direction. Also, the device was designed to detect a loss-of-frame sync for the frame sync input signal (Note, the loss-of-frame sync (TILOF) feature is not supported in version 3 of the device). The state of TILOC and TILOF (0x19) along with any changes to TILOCFD and TILOCFM (0x07 and 0x10) will be reported to the control system. Transmit Clock Frequency Provisioning The device must be provisioned (THSCLKTYPE[1:0], 0x3C) with the speed (155.52 MHz--bit, 38.88 MHz-- nibble, 19.44 MHz--byte) of the transmit clock. This information is needed to set the internal clock divider circuitry and determine valid output port modes (e.g., a byte clock input cannot support a serial output port at 155.52 Mbits/s).
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Maintenance Functions (continued)
Transmit Functions (continued)
Section Far-End Bit Error (SFEBE) The device will insert SFEBE in the transmitted M1 byte whenever there are bit errors in the received B2 bytes. This function can be inhibited (TSFEBEINH, 0x3E) and the default value inserted, either all ones (SDH) or all zeros (SONET). The device can insert a continuous error into the M1 byte under user control (TSFEBEEINS, 0x4D). SFEBE will be inserted into the M1 byte as defined in Figure 3.
23 (MSB) Z2-1 Z2-2 M1 0 (LSB)
7 (MSB) SECTION FEBE
0 (LSB)
5-5295(F)
Figure 3. SFEBE Location The values for SFEBE are summarized in Table 12. Table 12. SFEBE Values Section or Line FEBE Number of B2 Bit Errors in the Receive Signal 00000000 00000001 00000010 ... 00010111 00011000 00011001 ... 11111110 11111111 (SDH) 00000000 (SONET) Section FEBE not supported (no errors) 0 (no errors) 1 2 ... 23 24 No errors
Agere Systems Inc.
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Maintenance Functions (continued)
Transmit Functions (continued)
Path - Trace Byte (J1)--AU-4 Mode Only The device will continuously insert a 64-byte sequence (TJ1DINS[64--1][7:0], 0x80--0xBF) into the outgoing STM-1 (AU-4) signal when the TJ1INS signal is active; otherwise, all zeros will be inserted into this byte. Path - Signal Label Byte (C2)--AU-4 Mode Only The device will allow data to be inserted into the outgoing C2 byte under software control (TC2DINS[7:0], 0x46). Path - G1 Status Byte (PFEBE (REICNT))--AU-4 Mode Only The G1 byte contains the PFEBE (B3 errors) as shown in Table 13. Table 13. G1 Byte--AU-4 Mode Only MSB (7) 6 5 4 3 RDI-P 2 1 LSB (0)
PFEBE[3:0] Valid values (0 to 8) all others indicate no errors
111 (SDH) or 000 (SONET)
The device will insert PFEBE in the transmitted G1 byte whenever there are bit errors in the received B3 byte. This function can be inhibited (TPFEBEINH, 0x3E) and the default value inserted, either all ones (SDH) or all zeros (SONET). The device can insert a continuous error into the G1 PFEBE[3:0] byte under user control (TPFEBEEINS, 0x4D). The values for PFEBE are summarized in Table 14. Table 14. PFEBE Values Section or Line FEBE Number of B3 Bit Errors in the Receive Signal 0000 0001 0010 ... 0111 1000 1001 ... 1111 0 (no errors) 1 2 ... 7 8 No errors
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Maintenance Functions (continued)
Transmit Functions (continued)
Path - G1 Status Byte (RDI-P)--AU-4 Mode Only The G1 byte contains the RDI-P bit as shown in Table 13. Path RDI is inserted automatically under hardware control. Each failure contribution can be excluded from the generation equation by setting the appropriate inhibit bit. TPRDIINT = ((RILOC AND TRILOC_PRDIINH), 0x4B, OR (RHSLOS AND TRHSLOS_PRDIINH), 0x4B, OR (RHSOOF AND TRHSOOF_PRDIINH), 0x4B, OR (RHSLOF AND TRHSLOF_PRDIINH), 0x4B, OR (RLAISMON AND TRLAISMON_PRDIINH), 0x4B, OR (RPAIS1 AND TRPAIS1_PRDIINH), 0x4B, OR (RLOP1 AND TRLOP1_PRDIINH), 0x4B, OR TPRDIINS (software insert)); (See 0x1A, 0x1B, 0x4B.) PRDI can be forced, via microprocessor control, by setting TPRDIINS to a logic 1. Path - User Channel Byte (F2)--AU-4 Mode Only Via microprocessor control of the (TF2DINS[7:0], 0x47), data information may be inserted into the outgoing F2 byte. Path - Growth Byte (Z3)--AU-4 Mode Only Via microprocessor control of the (TZ3DINS[7:0], 0x48), data information may be inserted into the outgoing Z3 byte. Path - Tandem Connection Byte (Z5)--AU-4 Mode Only Via microprocessor control of the (TZ5DINS[7:0], 0x49), data information may be inserted into the outgoing Z5 byte. Pseudorandom Test Pattern Insert--AU-4 Mode Only A pseudorandom test sequence can be inserted into any selected (TSTGEN_PSEL[1:0], 0x4E) TUG-3 within the AU-4 signal. The pattern can be selected from the following two equations: Q23 + Q17 + 1 or Q15 + Q14 + 1 (TPAT23or15, 0x4E). A one shot is provided to inject eight (8) errors into the selected pseudorandom sequence (TSTGENE8INS, 0x04). A value of zero in the TSTGEN_PSEL[1:0] register disables this function.
Agere Systems Inc.
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Maintenance Functions (continued)
Transmit Functions (continued)
Output Offset The device will output the STS-3/STM-1 (AU-4) frame a programmable number of clock cycles from the input frame sync. These registers allow movement of the output frame with a granularity of one high-speed clock cycle. The values programmed in (TLBITCNT[2:0], TLSTS1CNT[1:0], TLCOLCNT[6:0], TLROWCNT[3:0], 0x53, 0x54) must be within the valid ranges for the mode selected (see Table 15). See Table 56 on page 77 for more details. Table 15. Value Offset Load Values Mode BIT NIBBLE BYTE TLBITCNT[2:0] 0--7 0--1 0 TLSTS1CNT[1:0] 0--2 0--2 0--2 TLCOLCNT[6:0] 0--89 0--89 0--89 TLROWCNT[3:0] 0--8 0--8 0--8
Transmit Transport Overhead Access Channel (TTOAC) A transport overhead access channel (TOAC) is provided on-chip to provision the TOH portion of the outgoing SDH or SONET frame. The TOAC consists of the following signals:
I I I
A 5.184 MHz clock signal, sourced by the device (TTOACCLKO, TTOAC_CLKINV). A 5.184 Mbits/s data signal received by the device in the transmit direction (TTOACDATAI). An 8 kHz synchronization signal (TTOACSYNCO), sourced by the device. The sync signal is normally low; during the last clock period of each frame coincident with the least significant bit of the eighty-first byte or during the first clock period of each frame coincident with the most significant bit of the first byte, the sync signal is high (TTOACSA1orEND, 0x4F).
An inhibit signal is provided through the control interface to place the clock and sync signals in a high-impedance state (TTOACINH, 0x4F). The data signal is partitioned into frames of 81 bytes. The frame repetition rate is 8 kHz. Each byte consists of 8 bits that are received most significant bit first. The MSB of the first byte of each frame contains an odd/even parity bit over the 648 bits of the previous frame. The remaining 7 bits of this byte are not specified. Bytes shown in Table 16 summarize the access capabilities of the transmit TOAC. Bytes indicated in bold type are not specified in the standard, but are labeled here for clarity. X symbols indicate don't cares. Table 16. Transport Overhead Byte Access--Transmit Direction OH Pty X D1 X X D4 D7 D10 S1 36 X B1-2 D1-2 X X D4-2 D7-2 D10-2 Z1-2 X B1-3 D1-3 X X D4-3 D7-3 D10-3 Z1-3 X E1 D2 X X D5 D8 D11 Z2 X E1-2 D2-2 X K1-2 D5-2 D8-2 D11-2 Z2-2 X E1-3 D2-3 X K1-3 D5-3 D8-3 D11-3 X X F1 D3 X X D6 D9 D12 E2 X F1-2 D3-2 X K2-2 D6-2 D9-2 D12-2 E2-2 X F1-3 D3-3 X K2-3 D6-3 D9-3 D12-3 E2-3 Agere Systems Inc.
Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Maintenance Functions (continued)
Transmit Functions (continued)
OH Parity An event indication is provided at the control interface if an overhead parity error occurs. Odd/even parity is checked (TTOAC_OEPMON, TTOAC_PERRM, TTOAC_PERRE, 0x4F, 0x10, 0x07). D1--D3, D4--D12, E1, E2, F1, Z1, Z2 Overhead Bytes Table 17 summarizes the insertion options for the specified overhead bytes. The device allows (1) the default value for unused SDH or SONET bytes to be inserted, or (2) the transmit TOAC values to be inserted, or (3) the received STS-1/AU-3 value to be inserted into the outgoing STS-3 frame. Table 17. TTOAC Control Bits Overhead Bytes Control Bits1 00 (Default) or 11 D1--D3 D4--D12 E1 E2 F1 S1, Z1-2, Z1-3 Z2, Z2-2 B1-2, B1-3 E1-2, E1-3 F1-2, F1-3 D1-2, 3 to D3-2, 3 K1-2, K1-3 K2-2, K2-3 D4-2, 3 to D12-2, 3 E2-2, E2-3
1. See Address 0x50, 0x51 for control bits.
Values 01 TTOAC Data 10 Pass Through Associated STS-1/AU-3 Data
TTOAC_D1TO3[1:0] TTOAC_D4TO12[1:0] TTOAC_E1[1:0] TTOAC_E2[1:0] TTOAC_F1[1:0] TTOAC_Z1[1:0] TTOAC_Z2[1:0] TTOAC_INS[1:0]
SDH (1s) or SONET (0s) Default Values
SDH (1s) or SONET (0s) Default Values
TTOAC
Pass Through Associated STS-1/AU-3 Data
Agere Systems Inc.
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Maintenance Functions (continued)
Receive Functions
A number of the receive maintenance functions require a continuous N times detection (CNTD) of a signal to change an alarm status. All of these continuous N times detect signals require not only that the monitored signal be consistent for N consecutive frames, but also that the frame bytes, A1 and A2, be error free for all N frames before the status can be updated. If there are any errors in the framing pattern, then the consecutive N times detection counters must be reset to 0. N can range from 3 to 15. There is also a signal (CNTDB1SEL, 0x5F) that will cause these continuous N times detection counters to be reset to 0 if there are any errors in the received B1 byte. Continuous N Times Detect B1 Error Reset Enable The following CNTD monitors are affected by this control bit (CNTDB1SEL): 1. AIS-L (K2[2:0] = 111) 2. RDI-L (K2[2:0] = 110) 3. K2MON (K2[2:0]) 4. APSMON (K1[7:0], K02[7:3]) Receive Loss of Clock The device will detect a receive loss-of-clock (RILOC, 0x1B) condition for the clock input and notify the control system of any changes to this condition (RILOCD, 0x0A, and RILOCM, 0x13). Insertion of Line AIS (Automatic/Manual) The device will write Line AIS into each STS-1/AU-3 output signal if either the appropriate alarms occur or the software insert bit is active. LAIS_COMMON = ((RILOC AND RRILOC_AISINH) OR (RRHSOOF AND RHSOOF_AISINH) OR (RHSLOF AND RRHSLOF_AISINH) OR (RHSLOS AND RRHSLOS_AISINH) OR (LAISMON AND RRLAISMON_AISINH)); (See 0x1B, 0x58.) If (RLAISINS[3--1] = 1 OR LAIS_COMMON = 1), then insert Line AIS on the selected output. When a RILOC condition exists, the transmit clock is used to generate the Line AIS signal downstream, if possible. Insertion of Path AIS (Automatic) The device will write Path AIS into each STS-1/AU-3 output signal if the appropriate alarms occur. PAIS_COMMON[3--1] = ((PAIS[3--1] OR LOP[3--1]) AND PAISLOP_AISINH) If (PAIS_COMMON[3--1] = 1), then insert Path AIS on the appropriate output. (PAIS consists of writing all ones into the H1, H2, H3 bytes, and into the entire payload.) B1 BIP-8 Parity The device will perform B1 (BIP-8) calculation and error checking in the receive path. The device will allow access to the B1 errored bit/block (one block is equal to one frame) count (BITBLOCKCNT, 0x34, RHSB1ECNT[15:0], 0x8D-0x8E). This counter will update when LATCH_CNT transitions from a logic 0 to a logic 1. 38 Agere Systems Inc.
Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Maintenance Functions (continued)
Receive Functions (continued)
B2 BIP-24 Parity The device will perform B2 (BIP-24) calculation and error checking. The device will allow access to the B2 errored bit/block (one block is equal to one frame) count (BITBLOCKCNT, 0x34, RHSB2ECNT[16:0], Page 1 - 0x8F-- 0x91). This counter will update when LATCH_CNT, 0x04 transitions from a logic 0 to a logic 1. Signal Degrade BER Algorithm A signal degrade state and change of state indication will be provided to the control interface (RHSSD, RHSSDD, RHSSDM, 0x1B, 0x0A, 0x13). This bit error rate algorithm can operate on either B1 or B2 errors (SDB1B2SEL, 0x83). Signal degrade is declared when SDLSet[3:0], Page 2 - 0x83 or more bit errors in SDNsSet[18:0], Page 2 - 0x8E--0x90 and frames occur SDMSet[7:0], Page 2 - 0x84 times out of SDBSet[11:0], Page 2 - 0x85--0x86 blocks (one block is equal to one measurement period of SDNsSet[18:0] frames), and it is removed when less than SDLClear[3:0], Page 2 - 0x8A bit errors in SDNsClear[18:0], Page 2 - 0x87--0x89 frames occur SDMClear[7:0], Page 2 - 0x8B times out of SDBClear[11:0], Page 2 - 0x8C--0x8D blocks. The above algorithm can detect bit error rates from 1 x 10-3 to 1 x 10-9. Signal Fail BER Algorithm A signal fail state and change of state indication will be provided to the control interface (RHSSF, RHSSFD, RHSSFM, 0x1B, 0x0A, 0x13). This bit error rate algorithm can operate on either B1 or B2 errors (SFB1B2SEL, Page 2 - 0x91). Signal fail is declared when SFLSet[3:0], Page 2 - 0x91 or more bit errors in SFNsSet[18:0], Page 2 - 0x8E--0x90 frames occur SFMSet[7:0], Page 2 - 0x92 times out of SFBSet[11:0], Page 2 - 0x93--0x94 blocks (one block is equal to one measurement period of SFNsSet[18:0] frames), and it is removed when less than SFLClear[3:0], Page 2 - 0x98 bit errors in SFNsClear[18:0], Page 2 - 0x96--0x98 frames occur SFMClear[7:0], Page 2 - 0x99 times out of SFBClear[11:0] Page 2 - 0x9A--0x9B blocks. The above algorithm can detect bit error rates from 1 x 10-3 to 1 x 10-9. Section Trace (J0, Z0-2, Z0-3) Byte Monitoring The device will monitor the section trace bytes (RJ0MON[7:0], RZ02MON[7:0], RZ03MON[7:0], RCDRLOC, 0x1E, 0x1F, 0x20, 0x1B) on the receive input. A new section trace value will be detected after CNTDJ0Z0[3:0], 0x5A and consecutive consistent occurrences of a new pattern in the section trace overhead bytes. Any changes to these bytes will be reported to the control system (RJ0Z0MOND, RJ0Z0MONM, 0x0C, 0x15). Fault Location Monitoring (F1MON) The device will monitor the fault location byte (RF1MON0[7:0], 0x21) on the receive input. A new fault location state will be detected after CNTDF1[3:0], 0x5A consecutive consistent occurrences of a new pattern in the F1 overhead byte. The device will also maintain a history of the previous valid F1 byte (RF1MON1[7:0], 0x22). Any changes to this byte will be reported to the control system (RF1MOND, RF1MONM, 0x0C, 0x15). Automatic Protection Switch (APS) Monitoring The device will monitor the K1 byte and the K2 byte (5 MSBs only) on the input side of the device receive path (RAPSMON[12:0], 0x23, 0x24). After CNTDAPS[3:0], 0x5B consecutive consistent occurrences of new K1 and K2 bytes, the device will notify the control system (RAPSMOND, RAPSMONM, 0x0B, 0x14).
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Maintenance Functions (continued)
Receive Functions (continued)
APS Babbling Monitor The device will monitor the APS bytes (K1[7:0], K2[7:3]) in the receive direction and report to the control interface (RAPSBABLEE, RAPSBABLEM, 0x0C, 0x15) when the K1 bytes are inconsistent. Inconsistent APS bytes are defined as CNTDAPSFRAME[3:0], 0x5C (Default = 12) successive frames, starting with the last frame containing previously consistent code, where no CNTDAPS[3:0], 0x5B (Default = 3) consecutive frames contain identical APS bytes. Line AIS (AIS-L) Monitoring The device will monitor line AIS on the receive input (RLAISMON, 0x1D). Line AIS will be detected after CNTDK2[3:0], 0x5B consecutive occurrences of the AIS-L pattern (xxxxx111) in the K2 overhead byte. Any changes to this byte will be reported to the control system (RLAISMOND, RLAISMONM, 0x0C, 0x15). Line Remote Defect Indication (RDI-L) Monitoring The device will monitor an RDI-L condition on the receive input (RLRDIMON, 0x1D). A Line RDI condition will be detected after CNTDK2[3:0] consecutive occurrences of the Line RDI pattern (xxxxx110) in the K2 overhead byte. Any changes to this byte will be reported to the control system (RLRDIMOND, RLRDIMONM, 0x0C, 0x15). K2 Byte Monitoring The device will monitor the K2 byte (3 LSBs only) on the input side of the receive direction (RK2MON[2:0], 0x23). After CNTDK2[3:0], 0x5B consecutive consistent occurrences of new K2 bits, the device will notify the control system (RK2MOND, RK2MONM, 0x0B, 0x14). Sync Status (S1) Byte Monitoring The device will monitor the sync trace byte (RS1MON[7:0], 0x25) on the receive input. A new sync trace value will be detected after CNTDS1[3:0], 0x5C consecutive consistent occurrences of a new pattern in the overhead bytes. Any changes to this byte will be reported to the control system (RS1MOND, RS1MONM, 0x0C, 0x15). Section FEBE (M1) Monitoring The device will monitor a Section FEBE condition (M1) on the receive input. The device will allow access to the Section FEBE errored bit/block (one block is equal to one frame) count (FEBEBITBLOCKCNT, 0x34, RSFEBECNT[17:0], Page 1 - 0x34, 0xA4, 0xA6). This counter will update when LATCH_CNT transitions from a logic 0 to a logic 1. AU-4 NPI (Null Pointer Indication) Monitoring The device will monitor the three NPI values in the incoming STM-1(AU-4) signal. When five consecutive mismatches occur (any one of the three NPI values are in error) separated in time by 125 s, the device will declare an NPI mismatch condition. An NPI match condition is declared when two consecutive matches occur (all three NPI values match), separated in time by 125 s. The delta, mask, and state bits are RHSNPIMISD, RHSNPIMISM, RHSNPIMIS, 0x0D, 0x16, 0x1D, respectively.
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Maintenance Functions (continued)
Receive Functions (continued)
STM-1(AU-4) H4 Multibyte Monitor The device will monitor the path H4 byte for correct multibyte sequence. Each time the expected value mismatches with the received value, an event indication is set. When a mismatch occurs, the device accepts the new value plus 1 as the expected value for the next frame. The event and mask bits are RHSH4MISE, RHSH4MISM, 0x0D, 0x16. Path Trace Byte (J1) Monitoring The device will monitor the path trace byte (RJ1MON[64--1][7:0], 0xC0--0xFF) on the receive input. Only one J1 byte can be monitored (J1PSELMON[1:0], 0x56) out of the three possible J1 bytes. The device will store a 64-byte sequence and declare a mismatch each time the incoming value does not agree with the stored value (RJ1MISE, RJ1MISM, 0x0C, 0x15). Path Signal Label (C2) Monitoring The device will monitor the C2 bytes on the receive input (RC2MON[3--1][7:0], 0x28, 0x27, 0x26). After CNTDC2[3:0], 0x5D consecutive consistent occurrences of a new C2 byte, the device will notify the control system (RC2MOND[3--1], RC2MONM[3--1], 0x0D, 0x16). Path FEBE (G1) Byte Error Count The device will monitor for a path FEBE condition (G1[7:4]) on the input signal. The device will allow access to the path FEBE errored bit/block (one block is equal to one frame) count (FEBEBITBLOCKCNT, RPFEBECNT[3--1][15:0], 0x34, 0xA7--0xAC). These counters will update when LATCH_CNT, 0x04 transitions from a logic 0 to a logic 1. Path RDI (Path Yellow (G1[3] or Enhanced Failure Code (G1[3:1]))) The device will monitor the G1 bytes for path yellow condition or for an enhanced failure code (RRDI_MPYorEFC, 0x55) on the receive input (RRDIP[3--1][2:0], 0x32, 0x33). After CNTDG1[3:0], 0x5D consecutive consistent occurrences of a new G1 value, the device will notify the control system (RRDIPE[3--1], RRDIPM[3--1], 0x16). Path User Channel (F2) Monitoring The device will monitor the F2 byte (RF2MON[3--1][7:0], 0x29, 0x2A, 0x2B) on the receive input. A new value will be detected after CNTDF2[3:0], 0x5E consecutive consistent occurrences of a new pattern in the overhead bytes. Any change to this byte will be reported to the control system (RF2MOND[3--1], RF2MONM[3--1], 0x0E, 0x17). Path Growth Byte (Z3) Monitoring The device will monitor the Z3 bytes (RZ3MON[3--1][7:0], 0x2C, 0x2D, 0x2E) on the receive input. A new value will be detected after CNTDZ3[3:0], 0x5E consecutive consistent occurrences of a new pattern in the overhead bytes. Any change to this byte will be reported to the control system (RZ3MOND[3--1], RZ3MONM[3--1], 0x0E, 0x17). Path Tandem Connection Byte (Z5) Monitoring The device will monitor the Z5 bytes (RZ5MON[3--1][7:0], 0x31, 0x30, 0x2F) on the receive input. A new value will be detected after CNTDZ5[3:0], 0x5F consecutive consistent occurrences of a new pattern in the overhead bytes. Any change to this byte will be reported to the control system (RZ5MOND[3--1], RZ5MONM[3--1], 0x0F, 0x18). Agere Systems Inc. 41
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Maintenance Functions (continued)
Receive Functions (continued)
Test Pattern Drop (AU-4 Mode Only) The device will monitor a pseudorandom pattern (RPAT23or15, 0x60) on a per TUG-3 basis (RTSTDRP_PSEL[1:0], 0x60). The drop logic will provide an out-of-sync indication (RTSTDRP_OOS, 0x60) and an error count (RTSTDRP_ECNT[7:0], 0x61). This counter will hold at its maximum value and is not affected by the LATCH_CNT, 0x04 signal. The detector will transition to the in-sync-state after 32 consecutive matches occur. The detector will transition from the in-sync-state to the out-of-sync state if 32 consecutive errors are detected. STS-1/AU-3 Byte Error Insert or Overwrite Control This section summarizes the output error and overwrite capabilities on a per STS1/AU-3 basis. All path overhead bytes pass through from the input signal. Table 18. STS-1/AU-3 Overhead Control Control Signal per STS-1/ AU-3 Signal RA1A2ERREN, RA1A2ERRPEN[3--1], RA1A2ERRINS[4:0] (0x05, 0x62) RC1DINS[3--1][7:0] (0x68, 0x69, 0x6A) RB1ERRINS[3--1] (0x63) R_E1_PASS[3--1] (0x74) RF1INS[3--1] RF1DINS[3--1][7:0], R_F1_PASS[3--1] (0x64, 0x6B--0x6D, 0x74) R_D1TOD3_PASS[3--1] (0x75) RH1H2CRUPEN[3--1], RH1H2CRUPPorNDF (0x64) Bytes Affected/ Action Action
A1, A2 If (RA1A2ERREN = 0 1) then insert RA1A2ERRINS[4:0] Error Insert consecutive frame errors on the selected ports (RA1A2ERRPEN[3--1]) else insert correct framing pattern. C1 Always insert values.
B1 1 = insert error, 0 = insert normal value. Error Insert E1 1 = pass input data, 0 = insert default value.
F1 If (RF1INS = 1) then insert software value (RF1DINS) else if Software or (R_F1_PASS = 1) then pass input data Pass else set byte to the default value. D1 to D3 1 = pass input data, 0 = insert default value.
H1, H2 If (RH1H2CRUPPorNDF = 0 AND RH1H2CRUPEN = 1) then Error Insert continuously corrupt the pointer value else if (RH1H2CRUPPorNDF = 1 AND RH1H2CRUPEN = 1) then continuously send NDF (1001) pattern else pass input data. B2 1 = insert error, 0 = insert normal value. Error Insert K1, K2[7:3] If (RAPSBABLEINS = 1) then Error or continuously insert a nonconsistent K1K2 value Software else insert software value RAPSINS.
RB2ERRINS[3--1] (0x63) RAPSBABLEINS[3--1], RAPSINS[3--1][12:0] (0x66, 0x6E--0x73)
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Maintenance Functions (continued)
Receive Functions (continued)
Table 18. STS-1/AU-3 Overhead Control (continued) Control Signal per STS-1/ AU-3 Signal RLRDIINT[3--1] RTILOC_LRDIINH, RTLSLOF_LRDIINH[3--1], RTLSOOF_LRDIINH[3--1], RK2DINS[3--1][2:0] (0x1D, 0x67, 0x6E, 0x70, 0x72) R_D4TOD12_PASS[3--1] (0x75) R_S1_PASS[3--1] (0x76) RSFEBEINH[3--1] RSFEBEERRINS[3--1] (0x65) Bytes Affected/ Action Action
K2[2:0] RLRDIINT[3--1] = (TILOC AND TILOC_LRDIINH) OR Automatic/ (RTLSLOF[3--1] AND RTLSLOF_LRDIINH[3--1]) OR Software (RTLSOOF[3--1] AND RTLSOOF_LRDIINH[3--1]);1 If (all associated inhibit signals are active) then insert software value RK2DINS[3--1][2:0] else insert 110 pattern when RLRDIINT[3--1] is active else insert 000 pattern. D4 to D12 S1 M0 Automatic or Error Insert E2 1 = pass input data, 0 = insert default value. 1 = pass input data, 0 = insert default value. If (RSFEBEINH = 1) then inhibit the insertion of B2 errors and set the byte to the default value else if (RSFEBEERRINS = 1) then insert an error into the output byte else output B2 errors per frame from the associated transmit input. 1 = pass input data, 0 = insert default value.
R_E2_PASS[3--1] (0x76)
1. Software enable when all hardware inhibit signals are 1.
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Maintenance Functions (continued)
Receive Functions (continued)
Receive Transport Overhead Access Channel (RTOAC) A TOAC is provided on-chip to drop the TOH portion of the incoming SDH or SONET frame. The TOAC channel consists of the following signals: 1. 5.184 MHz clock signal, sourced by the device (RTOACCLKO, RTOAC_CLKINV). 2. A 5.184 Mbits/s data signal, sourced by the device (RTOACDATAO). 3. An 8 kHz synchronization signal, sourced by the device. The sync signal is normally low; during the last clock period of each frame coincident with the least significant bit of the eighty-first byte or coincident with the least significant bit of the first byte, the sync signal can go high (RTOACS_A1orEND, 0x4F). An inhibit signal is provided through the control interface to place the clock, data, and sync signal into a highimpedance state (RTOACINH, 0x4F). The data signal is partitioned into frames of 81 bytes. The frame repetition rate is 8 kHz. Each byte consists of 8 bits that are transmitted/received most significant bit first. The MSB of the first byte of each frame contains an odd/even parity bit over the 648 bits of the previous frame. The remaining 7 bits of this byte are not specified. Bytes shown in Table 19 summarize the access capabilities of the receive TOAC. Bytes indicated in bold type are not specified in the standard, but are labeled here for clarity. Table 19. Transport Overhead Byte Access--Receive Direction OH Pty B1 D1 H1-1 B2-1 D4 D7 D10 S1 OH Parity Even or odd parity can be inserted into the first bit of the MSB byte (RTOAC_OEPINS, 0x4F) of the TOAC outgoing frame. A1-2 B1-2 D1-2 H1-2 B2-2 D4-2 D7-2 D10-2 Z1-2 A1-3 B1-3 D1-3 H1-3 B2-3 D4-3 D7-3 D10-3 Z1-3 A2-1 E1 D2 H2 K1 D5 D8 D11 Z2-1 A2-2 E1-2 D2-2 H2-2 K1-2 D5-2 D8-2 D11-2 Z2-2 A2-3 E1-3 D2-3 H2-3 K1-3 D5-3 D8-3 D11-3 M1 J0 F1 D3 H3 K2 D6 D9 D12 E2 Z0-2 F1-2 D3-2 H3-2 K2-2 D6-2 D9-2 D12-2 E2-2 Z0-3 F1-3 D3-3 H3-3 K2-3 D6-3 D9-3 D12-3 E2-3
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Agere Systems Inc.
Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Typical Uses
Section and Line Termination Multiplex
Using the device without internal loopbacks results in a multiplex/demultiplex operation.
SPE OVERHEAD GENERATE
LOCAL CLOCK GENERATION
MICROPROCESSOR INTERFACE
OVERHEAD MONITOR CONTROL SIGNALS BUS CONTROL STS-1/AU-3 IN OVERHEAD MONITOR ADD SELECT/ MULTICAST LOGIC
OVERHEAD MONITOR
3:1 MUX LOGIC
STS-3/STM-1 (AU-4) OUT
TOAC INSERT TRANSMIT DIRECTION RECEIVE DIRECTION
CONTROL SIGNALS 1:3 BUS CONTROL STS-1/AU-3 OUT TOAC DROP DROP SELECT LOGIC DEMUX LOGIC TRANSPORT/PATH MONITOR FRAMER STS-3/STM-1 (AU-4) IN
5-5296 (F)
Figure 4. Line Termination Multiplex
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Typical Uses (continued)
Add/Drop Multiplex
Using the device with STS-1/AU-3 internal loopbacks results in an add/drop multiplex.
RECEIVE DIRECTION TRANSMIT DIRECTION OVERHEAD GENERATE
DROP SELECT LOGIC 1:3 DEMUX LOGIC BUS CONTROL LOGIC
STS-3 IN
FRAMER TRANSPORT MONITOR
ADD SELECT/ MULTICAST LOGIC
3:1 MUX LOGIC
STS-3 OUT
DROP SELECT LOGIC
STS-1/AU-3 OUT
STS-1/AU-3 IN
5-5297 (F)
Figure 5. Add/Drop Multiplex
Digital Cross Connect
Using the device with STS-3 internal loopback results in a digital cross connect.
OVERHEAD GENERATE STS-1/AU-3 #1 OUT
STS-1/AU-3 #1 IN
OVERHEAD MONITOR OVERHEAD MONITOR 3:1 MUX LOGIC FRAMER TRANSPORT MONITOR 1:3 DEMUX LOGIC DROP SELECT LOGIC
STS-1/AU-3 #2 OUT
STS-1/AU-3 #2 IN
STS-1/AU-3 #3 IN
OVERHEAD MONITOR
STS-1/AU-3 #3 OUT
5-5298 (F)
Figure 6. Digital Cross Connect
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface
Overview
The device is equipped with an asynchronous microprocessor interface that can operate with most commercially available microprocessors. Inputs MPMUX and MPMODE are used to configure this interface into one of four possible modes. The MPMUX setting selects either a multiplexed 8-bit address/data bus (AD[7:0]) or a demultiplexed 8-bit address bus (A[7:0]) and an 8-bit data bus (AD[7:0]). The MPMODE setting selects the associated set of registers within the device. Due to device flexibility, there are no default powerup or reset states. All read/write registers must be written by the microprocessor on system start-up to guarantee proper device functionality. The microprocessor interface can operate at speeds up to 32.768 MHz in interrupt-driven or polled modes without requiring any wait-states.
Microprocessor Configuration Modes
Table 20 highlights the four microprocessor modes controlled by the MPMUX and MPMODE inputs. Table 20. Microprocessor Configuration Modes Mode MODE 1 MODE 2 MODE 3* MODE 4 MPMODE 0 0 1 1 MPMUX 0 1 0 1 Address/Data Bus DeMUXed MUXed DeMUXed MUXed Generic Control, Data and Output Pin Names CS, AS, DS, R/W, A[7:0], AD[7:0], INT, DTACK CS, AS, DS, R/W, AD[7:0], INT, DTACK CS, ALE, RD, WR, A[7:0], AD[7:0], INT, RDY CS, ALE, RD, WR, AD[7:0], INT, RDY
* When the MPMODE3ALE input pin = 0, ALE is not used to retime the incoming address.
Microprocessor Interface Pinout Descriptions
The MODE [1--4] specific pin definitions are given in Table 21. Note that the microprocessor interface uses the same set of pins in all modes. Table 21. MODE [1--4] Microprocessor Pin Definitions Configuration MODE 1 Device Pin Name WR_DS RD_R/W Generic Pin Name DS R/W Pin Type Input Input Assertion Sense -- Function
Active-Low Data Strobe Read/Write R/W = 1 for Read R/W = 0 for Write Address Strobe
ALE_AS CS INT RDY_DTACK AD[7:0] A[7:0]
AS CS INT DTACK AD[7:0] A[7:0]
Input Input Output I/O Input
--
Active-Low Chip Select Active-Low Data Acknowledge -- -- Data Bus Address Bus
Output Active-High Interrupt
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Microprocessor Interface (continued)
Microprocessor Interface Pinout Descriptions (continued)
Table 21. MODE [1--4] Microprocessor Pin Definitions (continued) Configuration MODE 2 Device Pin Name WR_DS RD_R/W Generic Pin Name DS R/W Pin Type Input Input Assertion Sense -- Function
Active-Low Data Strobe Read/Write R/W = 1 for Read R/W = 0 for Write Address Strobe Interrupt
ALE_AS CS INT RDY_DTACK AD[7:0] MODE 3 WR_DS RD_R/W ALE_AS CS INT RDY_DTACK AD[7:0] A[7:0] MODE 4 WR_DS RD_R/W ALE_AS CS INT RDY_DTACK AD[7:0]
* Optional (MPMODE3ALE).
AS CS INT DTACK AD[7:0] WR RD ALE* CS INT RDY AD[7:0] A[7:0] WR RD ALE CS INT RDY AD[7:0]
Input Input Output Output I/O Input Input Input Input Output Output I/O Input Input Input Input Input Output Output I/O
-- ActiveHigh -- -- --
Active-Low Chip Select
Active-Low Data Acknowledge Address/Data Bus Read Address Latch Enable Interrupt Active-Low Write
Active-Low Chip Select ActiveHigh -- -- -- --
Active-Low Ready Data Bus Address Bus Read Address Latch Enable Interrupt
Active-Low Write
Active-Low Chip Select ActiveHigh --
Active-Low Ready Address/Data Bus
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface (continued)
Microprocessor Interface Register Architecture
The register bank architecture of the microprocessor interface is shown in Table 22. Addresses referred to in this section are given in decimal, with the hexadecimal representation in parentheses. Table 22. Device-Level Register Map
Addr D (Hex)
0(00) 1(01) 2(02) 3(03) 4(04) 5(05) 6(06) 7(07) 8(08) 9(09) 10(0A) 11(0B) 12(0C) 13(0D) 14(0E) 15(0F) INTN Mask Parameters--R/W 16(10) 17(11) 18(12) 19(13) 20(14) 21(15) 22(16) 23(17) 24(18) State and Value Parameters--RO 25(19) 26(1A) 27(1B) 28(1C) 29(1D) 30(1E) 31(1F) 32(20) 33(21) 34(22) 35(23) 36(24) 37(25) 38(26) 39(27) 40(28) 41(29) 42(2A) RAPSMON[12:8] RAPSMON[7:0] RS1MON[7:0] RC2MON1[7:0] RC2MON2[7:0] RC2MON3[7:0] RF2MON1[7:0] RF2MON2[7:0] TILOC TPRDIINT RCDRLOC RHSNPIMIS TILOF TLRDIINT RHSSF RLRDIMON TLSLOF3 TLSH4MIS3 RHSSD RPAIS3 RLAISMON TLSLOF2 TLSH4MIS2 RHSLOSEXTI RPAIS2 TLSLOF1 TLSH4MIS1 RHSLOS RPAIS1 TLSOOF3 TLSPTRMIS3 RHSLOF RLOP3 RLRDIINT3 TLSOOF2 TLSPTRMIS2 RHSOOF RLOP2 RLRDIINT2 TLSOOF1 TLSPTRMIS1 RILOC RLOP1 RLRDIINT1 RHSPARM RAPSMONM RAPSBABLEM RHSNPIMISM RHSSFM RK2MONM RLRDIMONM RHSH4MISM TILOCFM TLSLOFM3 TLSH4MISM3 RHSSDM RPAISM3 RLAISMONM RRDIPM3 RZ3MONM3 RRDIPM2 RZ3MONM2 RPAISM2 TLSLOFM2 TLSH4MISM2 TTOAC_PERRM TLSLOFM1 TLSH4MISM1 RHSLOSM RPAISM1 RJ1MISM RRDIPM1 RZ3MONM1 TLSPARM3 TLSOOFM3 TLSPTRMISM3 RHSLOFM RLOPM3 RS1MONM RC2MONM3 RF2MONM3 RZ5MONM3 TLSPARM2 TLSOOFM2 TLSPTRMISM2 RHSOOFM RLOPM2 RF1MONM RC2MONM2 RF2MONM2 RZ5MONM2 TSLSPARM1 TLSOOFM1 TLSPTRMISM1 RILOCM RLOPM1 RJ0Z0MONM RC2MONM1 RF2MONM1 RZ5MONM1 RHSPARE RAPSMOND RAPSBABLEE RHSNPIMISD RHSSFD RK2MOND RLRDIMOND RHSH4MISE TILOCFD TLSLOFD3 TLSH4MISD3 RHSSDD RPAISD3 RLAISMOND RRDIPD3 RZ3MOND3 RRDIPD2 RZ3MOND2 RPAISD2 TLSLOFD2 TLSH4MISD2 TA1A2ERREN RA1A2ERREN Controller Scratch Byte--R/W SCRATCH[7:0] Delta and Event Parameters--COR-RO TTOAC_PERRE TLSLOFD1 TLSH4MISD1 RHSLOSD RPAISD1 RJ1MISE RRDIPD1 RZ3MOND1 TLSPARE3 TLSOOFD3 TLSPTRMISD3 RHSLOFD RLOPD3 RS1MOND RC2MOND3 RF2MOND3 RZ5MOND3 TLSPARE2 TLSOOFD2 TLSPTRMISD2 RHSOOFD RLOPD2 RF1MOND RC2MOND2 RF2MOND2 RZ5MOND2 TLSPARE1 TLSOOFD1 TLSPTRMISD1 RILOCD RLOPD1 RJ0Z0MOND RC2MOND1 RF2MOND1 RZ5MOND1 TSTGENE8INS SFCLEAR DEVID[15:8] = 0x31 DEVID[7:0] = 0x55 DEVVER[7:0] = 0x00 One-Shot (0 to 1 Transition) Control Bit Parameters--Read/Write (R/W) SFSET SDCLEAR SDSET RSTCTL LATCH_CNT
Bit Number--Device (ANSI)* 7 (1) 6 (2) 5 (3) 4 (4) 3 (5) 2 (6) 1 (7) 0 (8)
INT Common Fixed Parameters--Read Only (RO)
CONCAT_STATE2[1:0]
CONCAT_STATE3[1:0] Receive Monitor Values--RO RJ0MON[7:0] RZ02MON[7:0] RZ03MON[7:0] RF1MON0[7:0] RF1MON1[7:0]
RK2MON[2:0]
* Shaded blocks are reserved for future or internal use.
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Microprocessor Interface (continued)
Microprocessor Interface Register Architecture (continued)
Table 22. Device-Level Register Map (continued)
Addr D (Hex)
43(2B) 44(2C) 45(2D) 46(2E) 47(2F) 48(30) 49(31) 50(32) 51(33) Mode Control--R/W 52(34) 53(35) Transmit Low-Speed Port 1 Input--R/W 54(36) 55(37) 56(38) 57(39) 58(3A) 59(3B) 60(3C) 61(3D) 62(3E) 63(3F) 64(40) 65(41) 66(42) 67(43) 68(44) 69(45) 70(46) 71(47) 72(48) 73(49) 74(4A) 75(4B) 76(4C) 77(4D) 78(4E) 79(4F) 80(50) 81(51) 82(52) 83(53) 84(54) -- RTOAC_CLKINV TPFEBEEINS TSFEBEEINS TH1H2CRUPEN[3--1]
RTOACS_A1orEND
Bit Number--Device (ANSI)* 7 (1) 6 (2) 5 (3) 4 (4)
RF2MON3[7:0] RZ3MON1[7:0] RZ3MON2[7:0] RZ3MON3[7:0] RZ5MON1[7:0] RZ5MON2[7:0] RZ5MON3[7:0] RRDIP2[2:0] RRDIP1[2:0] RRDIP3[2:0] RSONET_SDH RSTS3_AU4 MODE [1:0] - RO
FEBEBITBLOCKCNT
3 (5)
2 (6)
1 (7)
0 (8)
BITBLOCKCNT TLSCLKINV
TSONET_SDH TLSV1DISABLE
TSTS3_AU4 TLSVOEPAR TLSDSCR1
Low-Speed Transmit Common Control Signals--R/W
TSEL1[2:0] TLS_UNEQUIP1 TLS_LAISINS1 TSEL2[2:0] TLS_UNEQUIP2 TLS_LAISINS2 TSEL3[2:0] TLS_UNEQUIP3
THSCLKSEL_DORS TLSPTRMIS_AISINH2 TLSH4MIS_AISINH2 TLSPTRMIS_AISINH1 TLSH4MIS_AISINH1
TLSLOF_AISINH1
TLSOOF_AISINH1 TLSDSCR2
Transmit Low-Speed Port 2 Input--R/W TLSLOF_AISINH2 TLSOOF_AISINH2 TLSDSCR3
TLSPTRMIS_AISINH3 TLSH4MIS_AISINH3
Transmit Low-Speed Port 3 Input--R/W TLS_LAISINS3 THSPAROEG RHS2THSLB Transmit High-Speed Control Signals--R/W TSS[1:0] TPFEBEINH TSFEBEINH TJ1INS TS1INS TF1INS TJ0DINS[7:0] TZ02DINS[7:0] TZ03DINS[7:0] TF1DINS[7:0] TAPSINS[12:8] TAPSINS[7:0] TS1DINS[7:0] TC2DINS[7:0] TF2DINS[7:0] TZ3DINS[7:0] TZ5DINS[7:0] Transmit High-Speed Line RDI Insertion Inhibit Bits--R/W TLRDIINH TPRDIINS TRLOP1_PRDIINH TRHSSF_LRDIINH
TRPAIS1_PRDIINH TRLAISMON_LRDIINH TRHSLOF_LRDIINH TRHSOOF_LRDIINH TRHSLOS_LRDIINH
TLSLOF_AISINH3
TLSOOF_AISINH3
Transmit High-Speed Clock/Port Control--R/W THSSA1orEND THSCLKINV THSPTYPE[1:0] THSCHIZ THSCLKTYPE[1:0] THSSHIZ THSDHIZ THSSCR
TK2INS[2:0]
TRILOC_LRDIINH TRILOC_PRDIINH THSB1ERRINS
Transmit High-Speed Path RDI Insertion Inhibit Bits--R/W
TRLAISMON_PRDIINH TRHSLOF_PRDIINH TRHSOOF_PRDIINH TRHSLOS_PRDIINH
Transmit High-Speed Error Insert Control Parameters--R/W
THSB3ERRINS
THSB2ERRINS[3--1]
TA1A2ERRINS[4:0]
TAPSBABLEINS
TH1H2CRUPPorNDF
TPAT23or15 TTOAC_CLKINV TTOACSA1orEND
TSTGEN_PSEL[1:0] TTOAC_OEPMON TTOACINH
Receive/Transmit TOAC Control--R/W RTOAC_OEPINS RTOACINH TTOAC_E2[1:0] TTOAC_INS[1:0] TSTPHASE TLBITCNT[2:0] TLCOLCNT[3:0] TTOAC_E1[1:0] TTOAC_Z2[1:0] UPDWN CHOLD TTOAC_D4TO12[1:0] TTOAC_Z1[1:0] CNTEN BYPASS TTOAC_D1TO3[1:0] TTOAC_F1[1:0] CDR_TSTSHFTLD TLCOLCNT[6:4] TLROWCNT[3:0] CDR_TSTMODE
Transmit High-Speed Output Offset Control--R/W TLSTS1CNT[1:0]
* Shaded blocks are reserved for future or internal use.
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface (continued)
Microprocessor Interface Register Architecture (continued)
Table 22. Device-Level Register Map (continued)
Addr D (Hex)
85(55) 86(56) 87(57) 88(58) 89(59) 90(5A) 91(5B) 92(5C) 93(5D) 94(5E) 95(5F) 96(60) 97(61) 98(62) 99(63) 100(64) 101(65) 102(66) 103(67) 104(68) 105(69) 106(6A) 107(6B) 108(6C) 109(6D) 110(6E) 111(6F) 112(70) 113(71) 114(72) 115(73) 116(74) 117(75) 118(76) 119(77)-- 126(7E) 127(7F) PAGE[1:0] R_OVH_PASS R_Z2_PASS R_Z1_PASS[3--2] RAPSINS3[12:8] RAPSINS3[7:0] R_F1_PASS[3--1] R_D4TOD12_PASS[3--1] R_E2_PASS[3--1] R_E1_PASS[3--1] R_D1TOD3_PASS[3--1] R_S1_PASS[3--1] RAPSINS2[12:8] RAPSINS2[7:0] RK2DINS3[2:0] RAPSINS1[12:8] RAPSINS1[7:0] RK2DINS2[2:0]
RTILOC_LRDIINH RH1H2CRUPPorNDF RRLAISMON_AISINH
Bit Number--Device (ANSI)* 7 (1)
THS2RHSLB
6 (2)
RHSDSCR RLSSCR[3--1]
RRHSLOS_AISINH
5 (3)
RCONCATMODE
4 (4)
RRDI_MPYorEFC
RHSPORCDRSEL
3 (5)
RHSVOEPAR PAISLOP_AISINH
RRILOC_AISINH
2 (6)
RHSEDGE TLS2RLSLB
1 (7)
0 (8)
Receive High/Low-Speed Port Control--R/W RHSPTYPE[1:0] RSEL1[1:0] RLSCLKINV LOSDETCNT[10:8] RLSPAROEG J1PSELMON[1:0] RSEL3[1:0]
RRHSLOF_AISINH RRHSOOF_AISINH
RSEL2[1:0]
LOSDETCNT[7:0] Continuous N Times Detect Values--R/W CNTDF1[3:0] CNTDAPS[3:0] CNTDAPSFRAME[3:0] CNTDG1[3:0] CNTDF2[3:0] CNTDB1SEL
RTSTDRP_OOS RTSTDRP_ECNT[7:0]
CNTDJ0Z0[3:0] CNTDK2[3:0] CNTDS1[3:0] CNTDC2[3:0] CNTDZ3[3:0] CNTCIP_ICI[1:0] Receive Test Pattern Drop--R/W, RO RPAT23or15 Receive Low-Speed Output Overhead Control--R/W RTSTDRP_PSEL[1:0] CNTDZ5[3:0]
RLOCINH
RA1A2ERRPEN[3--1] RB2ERRINS[3--1] RH1H2CRUPEN[3--1] RSFEBEERRINS[3--1] RLAISINS[3--1] RTLSLOF_LRDIINH[3--1] RC1DINS1[7:0] RC1DINS2[7:0] RC1DINS3[7:0] RF1DINS1[7:0] RF1DINS2[7:0] RF1DINS3[7:0]
RA1A2ERRINS[4:0] RB1ERRINS[3--1] RF1INS[3--1] RSFEBEINH[3--1] RAPSBABLEINS[3--1] RTLSOOF_LRDIINH[3--1]
RK2DINS1[2:0]
* Shaded blocks are reserved for future or internal use.
Table 23. Page 0--J1 Byte Insert and Monitor
Addr D (Hex)
128 (80)-- 191 (BF) 192 (C0)--255 (FF)
Bit Number--Device (ANSI) 7 (1) 6 (2) 5 (3) 4 (4) 3 (5) 2 (6) 1 (7) 0 (8)
J1 Byte Transmit Insert--64 Bytes--R/W TJ1DINS[64--1][7:0] J1 Byte Receive Monitor--64 Bytes--RO RJ1MON[64--1][7:0]
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Microprocessor Interface (continued)
Microprocessor Interface Register Architecture (continued)
Table 24. Page 1--Error Counters
Addr D (Hex)
128(80) 129(81) 130(82) 131(83) 132(84) 133(85) 134(86) 135(87) 136(88) 137(89) 138(8A) 139(8B) 140(8C) 141(8D) 142(8E) 143(8F) 144(90) 145(91) 146(92) 147(93) 148(94) 149(95) 150(96) 151(97) 152(98) 153(99) 154(9A) 155(9B) 156(9C) 157(9D) 158(9E) 159(9F) 160(A0) 161(A1) 162(A2) 163(A3) 164(A4) 165(A5) 166(A6) 167(A7) 168(A8) 169(A9) 170(AA) 171(AB) 172(AC) RSFEBECNT[15:8] RSFEBECNT[7:0] RPFEBECNT1[15:8] RPFEBECNT1[7:0] RPFEBECNT2[15:8] RPFEBECNT2[7:0] RPFEBECNT3[15:8] RPFEBECNT3[7:0] RPTR_DEC3[7:0] Receive High-Speed Section/Path FEBE Counts--RO RSFEBECNT[17:16] RPTR_DEC2[7:0] RPTR_DEC3[10:8] RPTR_DEC1[7:0] RPTR_DEC2[10:8] RPTR_INC3[7:0] RPTR_DEC1[10:8] RPTR_INC2[7:0] RPTR_INC3[10:8] RPTR_INC1[7:0] RPTR_INC2[10:8] RHSB2ECNT[15:8] RHSB2ECNT[7:0] RHSB3ECNT1[15:8] RHSB3ECNT1[7:0] RHSB3ECNT2[15:8] RHSB3ECNT2[7:0] RHSB3ECNT3[15:8] RHSB3ECNT3[7:0] Receive High-Speed Pointer INCrement and DECrement Counters--RO RPTR_INC1[10:8] TLSB2ECNT1[15:8] TLSB2ECNT1[7:0] TLSB2ECNT2[15:8] TLSB2ECNT2[7:0] TLSB2ECNT3[15:8] TLSB2ECNT3[7:0] Receive High-Speed B1, B2, and B3 Error Counts--RO RHSB1ECNT[15:8] RHSB1ECNT[7:0] RHSB2ECNT[17:16]
Bit Number--Device (ANSI)* 7 (1) 6 (2) 5 (3) 4 (4) 3 (5) 2 (6) 1 (7) 0 (8)
Transmit Low-Speed B1 and B2 Error Counts--RO TLSB1ECNT1[15:8] TLSB1ECNT1[7:0] TLSB1ECNT2[15:8] TLSB1ECNT2[7:0] TLSB1ECNT3[15:8] TLSB1ECNT3[7:0] TLSB2ECNT1[17:16]
* Shaded blocks are reserved for future or internal use.
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface (continued)
Microprocessor Interface Register Architecture (continued)
Table 25. Page 2--BER Algorithm Parameters
Addr D (Hex)
128(80) 129(81) 130(82) 131(83) 132(84) 133(85) 134(86) 135(87) 136(88) 137(89) 138(8A) 139(8B) 140(8C) 141(8D) 142(8E) 143(8F) 144(90) 145(91) 146(92) 147(93) 148(94) 149(95) 150(96) 151(97) 152(98) 153(99) 154(9A) 155(9B) 156(9C)-- 255(FF) SFMClear[7:0] SFBClear[15:8] SFBClear[7:0] Invalid SFNsClear[15:8] SFNsClear[7:0] SFLClear[3:0] SFB1B2SEL SFMSet[7:0] SFBSet[15:8] SFBSet[7:0] SFNsClear[18:16] SFNsSet[15:8] SFNsSet[7:0] SFLSet[3:0] SDMClear[7:0] SDBClear[15:8] SDBClear[7:0] Signal Fail Set/Clear Control Registers--R/W SFNsSet[18:16] SDNsClear[15:8] SDNsClear[7:0] SDLClear[3:0] SDB1B2SEL SDMSet[7:0] SDBSet[15:8] SDBSet[7:0] SDNsClear[18:16] SDNsSet[15:8] SDNsSet[7:0] SDLSet[3:0]
Bit Number--Device (ANSI)* 7 (1) 6 (2) 5 (3) 4 (4) 3 (5) 2 (6) 1 (7)
SDNsSet[18:16]
0 (8)
Signal Degrade Set/Clear Control Registers--R/W
* Shaded blocks are reserved for future or internal use.
Agere Systems Inc.
53
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Microprocessor Interface (continued)
Register Description
This section gives a brief description of each register bit and its functionality. All algorithms are described in the main text of the document or in the maintenance section of the document. The abbreviations after each register indicate if the register is read only (RO), clear-on-read (COR), or read/write (R/W). Table 26. Register 0 (RO) Address Dec (Hex) 0 (0x00) Bit 0 Name INT Function Interrupt. The active-high bit is a copy of the INT pin. This bit is the ORing of all event and delta bits (registers 0x07--0x0F). An event or delta bit contribution can be inhibited from contributing to this bit by setting the appropriate mask bit (see Mask Bit Operation on page 28). Reset Default 0
Table 27. Registers 1--3 (RO) Address Dec (Hex) 1 (0x01) 2 (0x02) 3 (0x03) Bit 7--0 7--0 7--0 Name DEVID[15:8] DEVID[7:0] DEVVER[7:0] Function Device ID. Upper device ID byte of the number which uniquely identifies the device. Device ID. Lower device ID byte of the number which uniquely identifies the device. Device Version Number. Device version register will change each time the device is changed. Reset Default 0x31 0x55 0x03
Table 28. Registers 4, 5: One-Shot Register 0 1 (R/W) Address Dec (Hex) 4 (0x04) Bit 7 Name TA1A2ERREN Function Transmit A1/A2 Error Enable. Inserts framing errors into the output STS-3/STM-1 (AU-4) signal. The number of consecutive errors is controlled by TA1A2ERRINS[4:0], 0x4D. Test Generation 8 Error Insert. Inserts eight errors into the pseudorandom signal being inserted into the selected TUG-3 signal. Signal Fail Clear. Allows the signal fail algorithm to be forced into the normal state. Signal Fail Set. Allows the signal fail algorithm to be forced into the failed state. Signal Degrade Clear. Allows the signal degrade algorithm to be forced into the normal state. Signal Degrade Set. Allows the signal degrade algorithm to be forced into the failed state. Reset Default 0
4 (0x04)
6
TSTGENE8INS
0
4 (0x04) 4 (0x04) 4 (0x04) 4 (0x04)
5 4 3 2
SFCLEAR SFSET SDCLEAR SDSET
0 0 0 0
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface (continued)
Register Description (continued)
Table 28. Registers 4, 5: One-Shot Register 0 1 (R/W) (continued) Address Dec (Hex) 4 (0x04) Bit 1 Name RSTCTL Function Reset Control (Software). Resets the device. This reset has the same effect as the external RESET pin. This is a service affecting action. All state machines and registers bits will revert to their default values. Latch Count. Causes all counters to latch their values and clear their internal counters, except the test drop counter. These counters are large enough to hold at least one second's worth of data. Receive A1/A2 Error Enable. Inserts framing errors into the respective output STS-1/AU-3 signal. Reset Default 0
4 (0x04)
0
LATCH_CNT
0
5 (0x05)
7
RA1A2ERREN
0
Table 29. Register 6: Scratch Register (R/W) Address Dec (Hex) 6 (0x06) Bit 7--0 Name SCRATCH [7:0] Function Scratch Register. Allows the control system to verify read and write operations to the device without affecting device operation. Reset Default 0x00
Table 30. Registers 7--15: Delta/Event (COR-RO) Address Dec (Hex) 7 (0x07) Bit 7 Name TILOCFD Function Transmit Input Loss of Clock and Frame Delta. Delta bit indicates a change of state for the local clock (TILOC, 0x19) or frame sync (TILOF, 0x19). The delta bit clears when read. Its mask bit is TILOCFM, 0x10. Note: The TILOF state is not supported in version 3 of the device. Transmit Transport Overhead Access Channel (TOAC) Parity Error Event. Event register indicates a parity error was detected on the incoming transmit section overhead access channel. The bit will be cleared when read, but will be set again if the condition persists. Its mask bit is TTOAC_PERRM, 0x10. Transmit Low-Speed Parity Error Event (Input Port Number). Indicates a byte transfer parity error on the respective STS-1/AU-3 input. These bits will clear when read, but will be set again if the condition persists. Their mask bits are TLSPARM[3--1], 0x10. Reset Default 0
7 (0x07)
3
TTOAC_PERRE
0
7 (0x07)
2--0
TLSPARE[3--1]
000
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Microprocessor Interface (continued)
Register Map (continued)
Table 30. Registers 7--15: Delta/Event (COR-RO) (continued) Address Dec (Hex) 8 (0x08) Bit 5--3 Name TLSLOFD[3--1] Function Transmit Low-Speed Loss-of-Frame Delta. Delta bits indicate a change in state of the loss-of-frame (TLSLOF[3--1], 0x19) monitor on each STS-1/AU3 input. The associated mask bits are TLSLOFM[3--1], 0x10. Transmit Low-Speed Out-of-Frame Delta. Delta bits indicate a change in state of the out-of-frame (TLSOOF[3--1], 0x19) monitor on each STS-1/ AU-3 input. The associated mask bits are TLSOOFM[3--1], 0x11. Transmit Low-Speed H4 Mismatch Delta. Delta bits indicate a change in state of the H4 multiframe pointer mismatch (TLSH4MIS[3--1], 0x1A) monitor on each AU-3 input. The associated mask bits are TLSH4MISM[3--1], 0x12. Transmit Low-Speed Pointer Mismatch Delta. Delta bits indicate a change in state of the pointer value monitor (H1, H2) (TLSPTRMIS[3--1], 0x1A) on each AU-3 input. The associated mask bits are TLSPTRMISM[3--1], 0x12. Receive High-Speed Parity Error Event. Event bit indicates a parity error was detected on a nibble/ byte transfer on the STS-3/STM-1 (AU-4) input. Its mask bit is RHSPARM, 0x13. Receive High-Speed Signal Fail Delta. Receive High-Speed Signal Degrade Delta. Delta bits are set each time the signal fail and signal degrade state values change (RHSSF, 0x1B, RHSSD, 0x1B), respectively. The associated mask bits are RHSSFM, 0x13 and RHSSDM, 0x13. Receive High-Speed Loss-of-Signal Delta. Delta bit indicates a change in state (RHSLOS, RHSLOSEXTI, 0x1B) when a loss of signal is detected. It clears on the incoming STS-3/STM-1 (AU-4) input. The RHSLOSEXTI is an external input from a device pin. RHSLOS is an internal indicator monitoring for a consecutive zero/ones pattern in the unscrambled data input. Its mask bit is RHSLOSM, 0x13. Reset Default 000
8 (0x08)
2--0
TLSOOFD[3--1]
000
9 (0x09)
5--3
TLSH4MISD[3--1]
000
9 (0x09)
2--0
TLSPTRMISD[3--1]
000
10 (0x0A)
7
RHSPARE
0
10 (0x0A) 10 (0x0A)
6 5
RHSSFD RHSSDD
0 0
10 (0x0A)
3
RHSLOSD
0
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface (continued)
Register Map (continued)
Table 30. Registers 7--15: Delta/Event (COR-RO) (continued) Address Dec (Hex) 10 (0x0A) Bit 2 Name RHSLOFD Function Receive High-Speed Loss-of-Frame. Delta bit indicates a change in state (RHSLOF), 0x1B when a loss of frame is detected. It clears on the incoming STS-3/STM-1 (AU-4) input. Its mask bit is RHSLOFM, 0x13. Receive High-Speed Out-of-Frame Delta. Delta bit indicates a change in state (RHSOOF, 0x1B) when an out of frame is detected. It clears on the incoming STS-3/STM-1 (AU-4) input. Its mask bit is RHSOOFM, 0x13. Receive Input Loss-of-Clock Delta. Delta bit indicates a change in state (RILOC, 0x1B) of the receive STS-3/STM-1 (AU-4) input clock. Its mask bit is RILOCM, 0x13. Receive APS (K1, K2 bytes) Monitor Delta. Delta bit indicates a change in state (RAPSMON[12:0], 0x23--24) when a new consistent value is detected (CNTDAPS[3:0], 0x5B) in the incoming K1 and K2[7:3] bits of the input STS-3/STM-1 (AU-4) frame. Its mask bit is RAPSMONM, 0x14. Receive K2 [2:0] Monitor Delta. This feature is not supported in version 3 of the device. Receive Path AIS Delta. Delta bit indicates a change in state (RPAIS[3--1], 0x1C) when the pointer state machines declare Path AIS (all ones in the H1 and H2 bytes) on the receive STS-3/STM-1 (AU-4) signal. Its mask bit is RPAISM[3--1], 0x14. Only port 1 information is valid in AU-4 mode. Receive Loss-of-Pointer Delta. Delta bit indicates a change in state (RLOP[3--1], 0x1C) when the pointer state machines declare loss of pointer on the receive STS-3/STM-1 (AU-4) signal. Its mask bit is RLOPM[3--1], 0x14. Only port 1 information is valid in AU-4 mode. Reset Default 0
10 (0x0A)
1
RHSOOFD
0
10 (0x0A)
0
RILOCD
0
11 (0x0B)
7
RAPSMOND
0
11 (0x0B) 11 (0x0B)
6 5--3
RK2MOND RPAISD[3--1]
0 000
11 (0x0B)
2--0
RLOPD[3--1]
000
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Microprocessor Interface (continued)
Register Map (continued)
Table 30. Registers 7--15: Delta/Event (COR-RO) (continued) Address Dec (Hex) 12 (0x0C) Bit 7 Name RAPSBABLEE Function Receive APS Babble Event. Event bit indicates when an inconsistent APS value has been detected CNTDAPS[3:0], 0x5B times in the incoming CNTDAPSFRAME[3:0], 0x5C frames. Its mask bit is RAPSBABLEM, 0x15. Receive Line-RDI Monitor Delta. Delta bit indicates a change in state (RLRDIMON, 0x1D) when the pattern 110 is detected/not detected CNTDK2[2:0], 0x1B consecutive times in the incoming STS-3/STM-1 (AU-4) frame. Its mask bit is RLRDIMONM, 0x15. Receive Line-AIS Monitor Delta. Delta bit indicates a change in state (RLAISMON, 0x10) when the pattern 111 is detected/not detected CNTDK2[2:0], 0x5B consecutive times in the incoming STS-3/STM-1 (AU-4) frame. Its mask bit is RLAISMONM, 0x15. Receive J1 Mismatch Event. Event bit indicates a change in state in the received J1 64-byte sequence (RJ1MON[64--1][7:0], 0xC0--0xFF). Its mask bit is RJ1MISM, 0x15. Receive S1 (Sync Status) Byte Monitor Delta. Delta bit indicates a change in state (RS1MON[7:0], 0x25) when a consecutive and consistent new value (CNTDS1[3:0], 0x5C) is detected in the incoming S1 byte of the STS-3/STM-1 (AU-4) frame. Its mask bit is RS1MONM, 0x15. Receive F1 Byte Monitor Delta. Delta bit indicates a change in state (RF1MON1[7:0], 0x22, RF1MON0[7:0], 0x21) when a consecutive and consistent new value (CNTDF1[3:0], 0x5A) is detected in the incoming F1 byte of the STS-3/ STM-1 (AU-4) frame. State byte RF1MON0[7:0] is the current new value, RF1MON1[7:0] is the previous F1 value. Its mask bit is RF1MONM, 0x15. Reset Default 0
12 (0x0C)
6
RLRDIMOND
0
12 (0x0C)
5
RLAISMOND
0
12 (0x0C)
3
RJ1MISE
0
12 (0x0C)
2
RS1MOND
0
12 (0x0C)
1
RF1MOND
0
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface (continued)
Register Map (continued)
Table 30. Registers 7--15: Delta/Event (COR-RO) (continued) Address Dec (Hex) 12 (0x0C) Bit 0 Name RJ0Z0MOND Function Receive Composite J0, Z0-2, Z0-3 Monitor Delta. Delta bit indicates a change in state (RJ0MON[7:0], 0x1E, RZ02MON[7:0], 0x1F, RZ03MON[7:0], 0x20) when a consecutive and consistent new value (CNTDJ0Z0[3:0], 0x5A) is detected in the incoming J0, Z0-2, Z0-3, bytes of the STS-3/STM-1 (AU-4) frame. Its mask bit is RJ0Z0MONM, 0x15. Receive High-Speed Null Pointer Indicator (NPI) Delta. Delta bit indicates a change in state (RHSNPIMIS, 0x1D): a mismatch is declared when five consecutive mismatches occur separated in time by 125 s in the received NPI value, a match is declared when two consecutive valid NPI values (byte 1 = 10011011, byte 2 = 11100000) are received spaced 125 s apart in the STM-1 (AU-4) frame. Its mask bit is RHSNPIMISM, 0x16. Receive High-Speed H4 Mismatch Event. Event bit indicates when the received H4 value does not agree with the expected value. The sequence 00, 01, 10, and 11 should repeat in consecutive frames. When a mismatch occurs, the device will accept that new value + 1 as the expected value for the next frame. Its mask bit is RHSH4MISM, 0x16. Receive RDI-P (G1 Byte) Delta. Delta bit indicates a change in state (RRDIP[3--1][2:0], 0x32--0x33) when a consecutive and consistent new value (CNTDG1[3:0], 0x5D) is detected in the incoming G1[3:1] bits of the STS-3/STM-1 (AU-4) frame. Its mask bit is RRDIPM[3--1], 0x16. The device will either monitor G1 bit 3 as a path yellow (RRDI_MPYorEFC = 0) or G1 bits 3 down to 1 as an enhanced failure code (RRDI_MPYorEFC = 1) under software control. Only port 1 information is valid in AU-4 mode. Reset Default 0
13 (0x0D)
7
RHSNPIMISD
0
13 (0x0D)
6
RHSH4MISE
0
13 (0x0D)
5--3
RRDIPD[3--1]
000
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Microprocessor Interface (continued)
Register Map (continued)
Table 30. Registers 7--15: Delta/Event (COR-RO) (continued) Address Dec (Hex) 13 (0x0D) Bit 2--0 Name RC2MOND[3--1] Function Receive C2 (Signal Label) Monitor Delta. Delta bit indicates a change in state (RC2MON [3--1][7:0], 0x26--28) when a consecutive and consistent new value (CNTDC2[3:0], 0x5D) is detected in the incoming C2 bytes of the STS-3/ STM-1 (AU-4) frame. Its mask bit is RC2MONM[3--1], 0x16. Only port 1 information is valid in AU-4 mode. Receive Z3 (Growth) Monitor Delta. Delta bit indicates a change in state (RZ3MON[3--1][7:0], 0x2C--2E) when a consecutive and consistent new value (CNTDZ3[3:0], 0x5E) is detected in the incoming Z3 bytes of the STS-3/STM-1 (AU-4) frame. Its mask bit is RZ3MONM[3--1], 0x17. Only port 1 information is valid in AU-4 mode. Receive F2 (User Channel) Monitor Delta. Delta bit indicates a change in state (RF2MON[3--1][7:0], 0x29--2B) when a consecutive and consistent new value (CNTDF2[3:0], 0x5E) is detected in the incoming F2 bytes of the STS-3/STM-1 (AU-4) frame. Its mask bit is RF2MONM[3--1], 0x17. Only port 1 information is valid in AU-4 mode. Receive Z5 (Tandem Connection) Monitor Delta. Delta bit indicates a change in state (RZ5MON [3--1][7:0], 0x31) when a consecutive and consistent new value (CNTDZ5[3:0], 0x5F) is detected in the incoming Z5 bytes of the STS-3/STM-1 (AU-4) frame. Its mask bit is RZ5MONM[3--1], 0x18. Only port 1 information is valid in AU-4 mode. Reset Default 000
14 (0x0E)
5--3
RZ3MOND[3--1]
000
14 (0x0E)
2--0
RF2MOND[3--1]
000
15 (0x0F)
2--0
RZ5MOND[3--1]
000
Table 31. Registers 16--24: Mask Bits (R/W) Address Dec (Hex) 16 (0x10) 16 (0x10) 16 (0x10) Bit 7 3 2--0 Name TILOCFM TTOAC_PERRM TLSPARM[3--1] Function Transmit Input Loss-of-Clock and Frame Mask. See (addr 0x07) for description. Transmit TOAC Parity Error Mask. See (addr 0x07) for description. Transmit Low-Speed Parity Error Mask. See (addr 0x07) for description. Reset Default 0 0 000
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface (continued)
Register Map (continued)
Table 31. Registers 16--24: Mask Bits (R/W) (continued) Address Dec (Hex) 17 (0x11) 17 (0x11) 18 (0x12) 18 (0x12) 19 (0x13) 19 (0x13) 19 (0x13) 19 (0x13) 19 (0x13) 19 (0x13) 19 (0x13) 20 (0x14) 20 (0x14) 20 (0x14) 20 (0x14) 21 (0x15) 21 (0x15) 21 (0x15) 21 (0x15) 21 (0x15) 21 (0x15) 21 (0x15) Bit 5--3 2--0 5--3 2--0 7 6 5 3 2 1 0 7 6 5--3 2--0 7 6 5 2 3 1 0 Name TLSLOFM[3--1] TLSOOFM[3--1] TLSH4MISM[3--1] TLSPTRMISM[3--1] RHSPARM RHSSFM RHSSDM RHSLOSM RHSLOFM RHSOOFM RILOCM RAPSMONM RK2MONM RPAISM[3--1] RLOPM[3--1] RAPSBABLEM RLRDIMONM RLAISMONM RS1MONM RJ1MISM RF1MONM RJ0Z0MONM Function Transmit Low-Speed Loss-of-Frame Mask. See (addr 0x08) for description. Transmit Low-Speed Out-of-Frame Mask. See (addr 0x08) for description. Transmit Low-Speed H4 Mismatch Mask. See (addr 0x09) for description. Transmit Low-Speed Pointer Mismatch Mask. See (addr 0x09) for description. Receive High-Speed Parity Error Mask. See (addr 0x0A) for description. Receive High-Speed Signal Fail Mask. See (addr 0x0A) for description. Receive High-Speed Signal Degrade Mask. See (addr 0x0A) for description. Receive High-Speed Loss-of-Signal Mask. See (addr 0x0A) for description. Receive High-Speed Loss-of-Frame Mask. See (addr 0x0A) for description. Receive High-Speed Out-of-Frame Mask. See (addr 0x0A) for description. Receive Input Loss-of-Clock Mask. See (addr 0x0A) for description. Receive APS Monitor Mask. See (addr 0x0B) for description. Receive K2 Monitor Mask. See (addr 0x0B) for description. Receive Path AIS Mask. See (addr 0x0B) for description. Receive Loss-of-Pointer Mask. See (addr 0x0B) for description. Receive APS Babble Mask. See (addr 0x0C) for description. Receive Line RDI Monitor Mask. See (addr 0x0C) for description. Receive Line AIS Monitor Mask. See (addr 0x0C) for description. Receive S1 Monitor Mask. See (addr 0x0C) for description. Receive J1 Mismatch Mask. See (addr 0x0C) for description. Receive F1 Monitor Mask. See (addr 0x0C) for description. Receive J0, Z0-2, Z0-3 Monitor Mask. See (addr 0x0C) for description. Reset Default 000 000 000 000 0 0 0 0 0 0 0 0 0 000 000 0 0 0 0 0 0 0 61
Agere Systems Inc.
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Microprocessor Interface (continued)
Register Map (continued)
Table 31. Registers 16--24: Mask Bits (R/W) (continued) Address Dec (Hex) 22 (0x16) 22 (0x16) 22 (0x16) 22 (0x16) 23 (0x17) 23 (0x17) 24 (0x18) Bit 7 6 5--3 2--0 5--3 2--0 2--0 Name RHSNPIMISM RHSH4MISM RRDIPM[3--1] RC2MONM[3--1] RZ3MONM[3--1] RF2MONM[3--1] RZ5MONM[3--1] Function Receive High-Speed NPI Mismatch Mask. See (addr 0x0D) for description. Receive High-Speed H4 Mismatch Mask. See (addr 0x0D) for description. Receive RDI-P Mask. See (addr 0x0D) for description. Receive C2 Monitor Mask. See (addr 0x0D) for description. Receive Z3 Monitor Mask. See (addr 0x0E) for description. Receive F2 Monitor Mask. See (addr 0x0E) for description. Receive Z5 Monitor Mask. See (addr 0x0F) for description. Reset Default 0 0 000 000 000 000 000
Table 32. Registers 25--51: State Bits (RO) Address Dec (Hex) 25 (0x19) 25 (0x19) Bit 7 6 Name TILOC TILOF Function Transmit Input Loss-of-Clock (State). See (addr 0x07) for description. Transmit Input Loss-of-Frame (State). See (addr 0x07) for description. Note: This feature is not supported in version 3 of the device. Transmit Low-Speed Loss-of-Frame (State). See (addr 0x08) for description. Transmit Low-Speed Out-of-Frame (State). See (addr 0x08) for description. Transmit RDI-P Internal (State). State bit indicates when Path RDI is active. (Valid only in AU-4 mode.) Transmit RDI-L Internal (State). State bit indicates when Line RDI is active. Transmit Low-Speed H4 Mismatch (State). See (addr 0x09) for description. Transmit Low-Speed Pointer Mismatch (State). See (addr 0x09) for description. Receive Clock Data Recovery Loss-of-Clock (State). State bit indicates when the internal CDR clock is missing. This is an active-high signal. Receive High-Speed Signal Fail (State). See (addr 0x0A) for description. Receive High-Speed Signal Degrade (State). See (addr 0x0A) for description. Reset Default Undefined. Undefined.
25 (0x19) 25 (0x19) 26 (0x1A) 26 (0x1A) 26 (0x1A) 26 (0x1A) 27 (0x1B)
5--3 2--0 7 6 5--3 2--0 7
TLSLOF[3--1] TLSLOOF[3--1] TPRDIINT TLRDIINT TLSH4MIS[3--1] TLSPTRMIS[3--1] RCDRLOC
111 111 1 1 000 000 Undefined. 1 1
27 (0x1B) 27 (0x1B) 62
6 5
RHSSF RHSSD
Agere Systems Inc.
Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface (continued)
Register Map (continued)
Table 32. Registers 25--51: State Bits (RO) (continued) Address Dec (Hex) 27 (0x1B) 27 (0x1B) 27 (0x1B) 27 (0x1B) 27 (0x1B) 28 (0x1C) 28 (0x1C) 29 (0x1D) 29 (0x1D) 28 (0x1C) 29 (0x1D) Bit 4 3 2 1 0 5--3 2--0 7 6 7--6 4--3 Name RHSLOSEXTI RHSLOS RHSLOF RHSOOF RILOC RPAIS[3--1] RLOP[3--1] RHSNPIMIS RLRDIMON CONCAT_STATE [2--3][1:0] Function Receive High-Speed Loss-of-Signal (External). See (addr 0x0A) for description. Receive High-Speed Loss-of-Signal (State). See (addr 0x0A) for description. Receive High-Speed Loss-of-Frame (State). See (addr 0x0A) for description. Receive High-Speed Out-of-Frame (State). See (addr 0x0A) for description. Receive Input Loss-of-Clock (State). See (addr 0x0A) for description. Receive Path AIS (State). See (addr 0x0B) for description. Receive Loss-of-Pointer (State). See (addr 0x0B) for description. Receive High-Speed NPI Mismatch (State). See (addr 0x0D) for description. Receive RDI-L Monitor (State). See (addr 0x0C) for description. Concatenation Pointer State Machine State. State bits indicate the state of the concatenation state machine (LOPC = 10, AISC = 01, CONC = 00). These values only have meaning in the AU-4 mode and the RCONCATMODE bit (addr 0x55) set to the concatenation mode (1). Receive AIS-L Monitor (State). State bit indicates a consistent consecutive K2[2:0] value of 111 has been detected (CNTDK1[3:0]) times. Receive RDI-L Internal (State). State bits indicate when Line RDI conditions are active on a per STS1/AU-3 basis in the device receive path. Receive J0 Monitor Value. See (addr 0x0C) for description. Receive Z0-2 Monitor Value. See (addr 0x0C) for description. Receive Z0-3 Monitor Value. See (addr 0x0C) for description. Receive F1 Current Monitor Value. See (addr 0x0C) for description. Receive F1 Previous Monitor Value. See (addr 0x0C) for description. Receive K2 Monitor Value. See (addr 0x0B) for description. Reset Default Input pin value. 1 1 1 Undefined. 111 111 1 0 10
29 (0x1D)
5
RLAISMON
0
29 (0x1D)
2--0
RLRDIINT[3--1]
111
30 (0x1E) 31 (0x1F) 32 (0x20) 33 (0x21) 34 (0x22) 35 (0x23)
7--0 7--0 7--0 7--0 7--0 2--0
RJ0MON[7:0] RZ02MON[7:0] RZ03MON[7:0] RF1MON0[7:0] RF1MON1[7:0] RK2MON[2:0]
0x00 0x00 0x00 0x00 0x00 000
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Data Sheet April 2001
Microprocessor Interface (continued)
Register Map (continued)
Table 32. Registers 25--51: State Bits (RO) (continued) Address Dec (Hex) 35 (0x23) 36 (0x24) 37 (0x25) 38 (0x26) 39 (0x27) 40 (0x28) 41 (0x29) 42 (0x2A) 43 (0x2B) 44 (0x2C) 45 (0x2D) 46 (0x2E) 47 (0x2F) 48 (0x30) 49 (0x31) 50 (0x32) 50 (0x32) 51 (0x33) Bit 7--3 7--0 7--0 7--0 Name RAPSMON[12:8] RAPSMON[7:0] RS1MON[7:0] RC2MON[1--3][7:0] Function Receive APS Monitor Value. See (addr 0x0B) for description. Receive S1 Monitor Value. See (addr 0x0C) for description. Receive C2 Monitor Path Values. See (addr 0x0D) for description. Receive F2 Monitor Path Values. See (addr 0x0E) for description. Receive Z3 Monitor Path Values. See (addr 0x0E) for description. Receive Z5 Monitor Path Values. See (addr 0x0F) for description. Receive RDI-P Monitor Path Values (G1 Byte). See (addr 0x0D) for description. Reset Default 0000000 000000 0x00 0x00
7--0
RF2MON[1--3][7:0]
0x00
7--0
RZ3MON[1--3][7:0]
0x00
7--0
RZ5MON[1--3][7:0]
0x00
5--3 2--0 2--0
RRDIP2[2:0] RRDIP1[2:0] RRDIP3[2:0]
000
Table 33. Register 52: Mode Control (R/W) Address Dec (Hex) 52 (0x34) Bit 7 Name RSONET_SDH Function Reset Default
52 (0x34)
6
RSTS3_AU4
52 (0x34)
5--4
MODE [1:0]
0 Receive SONET or SDH Mode. Control bit, when set to a logic 0, puts the device receive path into the SONET mode; otherwise, the device receive path remains in SDH mode. For STS-1 mode, set both RSONET_SDH and RSTS3_AU4 to a logic 0, and tie the external mode control pins low. 0 Receive STS3 or AU4 Mode. Control bit, when set to a logic 0, puts the device receive path into the STS-3 mode (three STS-1 signals multiplexed into an STS-3 signal); otherwise, AU-4 mode (three AU3 signals multiplexed into an STM-1 (AU-4) signal). For STS-1 mode, set both RSONET_SDH and RSTS3_AU4 to a logic 0, and tie the external mode control pins low. Mode Value from External Pins (RO). Read-only Must be status bits allow monitoring of the external mode set to 10. control pins.
64
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface (continued)
Register Map (continued)
Table 33. Register 52: Mode Control (R/W) (continued) Address Dec (Hex) 52 (0x34) Bit 3 Name FEBEBITBLOCKCNT Function Far-End Block Error (FEBE) Bit or Block Count (Control). Control bit, when set to a logic 0, causes the FEBE counters to count bit errors; otherwise, count block errors (a block equals one frame). Bit or Block Error Count (Control). Control bit, when set to a logic 0, causes the counters to count bit errors; otherwise, count block errors (a block equals one frame). Transmit SONET or SDH. Control bit, when set to a logic 0, puts the device transmit path into the SONET mode; otherwise, SDH mode. Transmit STS3 or AU4 Mode. Control bit, when set to a logic 0, puts the device transmit path into the STS-3 mode (STS-3 signal demultiplexed into three STS-1 signals); otherwise, AU-4 mode (STM-1 (AU-4) signal demultiplexed into three AU-3 signals). Reset Default 0
52 (0x34)
2
BITBLOCKCNT
0
52 (0x34)
1
TSONET_SDH
0
52 (0x34)
0
TSTS3_AU4
0
Table 34. Register 53: Low-Speed Transmit Common Signals (R/W) Address Dec (Hex) 53 (0x35) Bit 2 Name TLSCLKINV Function Transmit Low-Speed Clock Invert Control. Control bit, when set to a logic 1, causes the output clock to be inverted; otherwise, do not invert the output clock before leaving the device. Transmit Low-Speed V1 Disable Control. Control bit, when set to a logic 1, disables the generation of V1 time signal on the transmit low-speed bus interface. Transmit Low-Speed Verify Odd or Even Parity. Control bit, when set to a logic 0, causes odd parity to be verified per byte transfer per STS-1/AU-3 input; otherwise, even parity is verified. Reset Default 0
53 (0x35)
1
TLSV1DISABLE
0
53 (0x35)
0
TLSVOEPAR
0
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Microprocessor Interface (continued)
Register Map (continued)
Table 35. Register 54--59: Transmit Low-Speed Port Input Control (R/W) Address Dec (Hex) 54 (0x36) 56 (0x38) 58 (0x3A) 54 (0x36) 56 (0x38) 58 (0x3A) 55 (0x37) 57 (0x39) 59 (0x3B) Bit 7--5 Name TSEL[1--3][2:0] Function Transmit Select Control. Control bits allow input selection and loopback operation to occur on a per STS-1/AU-3 input basis (see Table 5, Input Select Control, on page 17). Transmit Low-Speed Descramble Control. Control bit, when set to a logic 1, causes the selected STS-1/AU-3 input signal to be descrambled. Transmit Low-Speed Unequipped Insert Control. Control bit, when set to a logic 1, causes an unequip signal to be generated in the selected STS-1/AU-3 time slot in the STS-3/STM-1 (AU-4) output signal; normal data is sent when set to a logic 0. Only TLS_UNEQUIP1 is used in AU-4 mode. Transmit Low-Speed Line AIS Insert Control. Control bit, when set to a logic 1, causes an AIS signal to be inserted into the selected STS-1/TUG-3 time slot in the STS-3/STM-1 (AU-4) output signal; normal data is sent when set to a logic 0. Only TLS_LAISINS1 is used in AU-4 mode. Transmit Low-Speed Pointer Mismatch AIS Inhibit Control. Control bit, when set to a logic 1, causes the associated failure not to contribute to the automatic insertion of AIS-L in the associated output time slot; otherwise, allow the associated alarm to contribute to the generation of AIS-L. Transmit Low-Speed H4 Mismatch AIS Inhibit Control. Same as above. Reset Default 010 001 000 0
0
TLSDSCR[1--3]
7
TLS_UNEQUIP[1--3]
0
55 (0x37) 57 (0x39) 59 (0x3B)
6
TLS_LAISINS[1--3]
0
55 (0x37) 57 (0x39) 59 (0x3B)
3
TLSPTRMIS_AISINH [1--3]
1
55 (0x37) 57 (0x39) 59 (0x3B) 55 (0x37) 57 (0x39) 59 (0x3B) 55 (0x37) 57 (0x39) 59 (0x3B)
2
TLSH4MIS_AISINH [1--3]
1
1
TLSLOF_AISINH[1--3] Transmit Low-Speed Loss-of-Frame AIS Inhibit Control. Same as above. TLSOOF_AISINH[1--3] Transmit Low-Speed Out-of-Frame AIS Inhibit Control. Same as above.
1
0
0
66
Agere Systems Inc.
Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface (continued)
Register Map (continued)
Table 36. Registers 60, 61: Transmit High-Speed Clock/Port Control (R/W) Address Dec (Hex) 60 (0x3C) Bit 7 Name THSCLKSEL_DorS Function Transmit High-Speed Clock Select Differential or Single-Ended Inputs. Control bit, when set to a logic 0, selects the differential clock and sync inputs (THSSCLKIT/C (pins 143, 142), THSSJ0J1V1IT/C (pins 140, 139)) for driving the transmit direction of the device; otherwise, the single-ended inputs (THSCLKI, THSJ0J1V1I) are selected. Transmit High-Speed Parity Odd or Even Generation. Control bit, when set to a logic 0, causes odd parity to be inserted in nibble/parallel mode per clock transfer on the STS-3/STM-1 (AU-4) output; a logic 1 causes even parity to be generated. Transmit High-Speed A1 or End Sync Alignment. Control bit, when set to a logic 0, causes the output sync to be coincident with the first bit, nibble, or byte of the outgoing frame; a logic 1 causes the sync to be coincident with the last bit, nibble, or byte of the frame. Transmit High-Speed Clock Invert. Control bit, when set to a logic 1, causes the output clock to be inverted, a logic 0 doesn't effect the clock. Transmit High-Speed Port Type. Control bits control the type of output port (STS-3/STM-1 (AU-4): 00 = serial, 01 = nibble, 10 = byte mode). Transmit High-Speed Clock Type. Control bits control the type of transmit clock being provided to the device: 00 = serial clock (155.52 MHz), 01 = nibble clock (38.88 MHz), 10 = byte clock (19.44 MHz). Reset Default 0
60 (0x3C)
6
THSPAROEG
0
60 (0x3C)
5
THSSA1orEnd
0
60 (0x3C)
4
THSCLKINV
0
60 (0x3C)
3--2
THSPTYPE[1:0]
00
60 (0x3C)
1--0
THSCLKTYPE[1:0]
00
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Microprocessor Interface (continued)
Register Map (continued)
Table 36. Registers 60, 61: Transmit High-Speed Clock/Port Control (R/W) (continued) Address Dec (Hex) 61 (0x3D) Bit 7 Name THSSCR Function Transmit High-Speed Scramble Enable. Control bit, when set to a logic 1, causes the output STS-3/ STM-1 (AU-4) signal to be scrambled; the signal is not scrambled if set to a logic 0. Receive High-Speed to Transmit High-Speed Loopback Control. Control bit, when set to a logic 1, causes the receive STS-3/STM-1 (AU-4) input signal to be looped back to the transmit high-speed output; loopback is disabled when set to a logic 0. Transmit High-Speed Clock High-Impedance (Control). Control signal, when set to a logic 1, causes the output STS-3/STM-1 (AU-4) clock to be placed in a high-impedance state; a logic 0 enables the output driver. Transmit High-Speed Sync High-Impedance (Control). Control signal, when set to a logic 1, causes the output STS-3/STM-1 (AU-4) sync signal to be placed in a high-impedance state; a logic 0 enables the output driver. Transmit High-Speed Data High-Impedance (Control). Control signal, when set to a logic 1, causes the output STS-3/STM-1 (AU-4) data signals to be placed in a high-impedance state; a logic 0 enables the output drivers. Reset Default 0
61 (0x3D)
6
RHS2THSLB
0
61 (0x3D)
2
THSCHIZ
0
61 (0x3D)
1
THSSHIZ
0
61 (0x3D)
0
THSDHIZ
0
Table 37. Register 62: Transmit High-Speed Control Signals (R/W) Address Dec (Hex) 62 (0x3E) Bit 7--6 Name TSS[1:0] Function Transmit SS (Bits). These bits are used in the STS-1 mode to set the SS bits when an unequipped signal is being generated. Transmit Path FEBE Inhibit. Control bit, when set to a logic 1, disables hardware insertion of Path FEBE (B3 errors) in the outgoing STM-1 (AU-4) frame G1 byte; a logic 0 enables hardware insertion of PFEBE. Only valid in AU-4 mode. Transmit Section FEBE Inhibit. Control bit, when set to a logic 1, disables hardware insertion of Section FEBE (B2 errors) in the outgoing STS-3/STM-1 frame M1 byte; a logic 0 enables hardware insertion of SFEBE. Reset Default 00
62 (0x3E)
4
TPFEBEINH
0
62 (0x3E)
3
TSFEBEINH
0
68
Agere Systems Inc.
Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface (continued)
Register Map (continued)
Table 38. Register 62, and Page 0, Registers 128--191: Transmit High-Speed J1 Insert (R/W) Address Dec (Hex) 62 (0x3E) Bit 2 Name TJ1INS Function Transmit J1 Insert (Control). Control bit, when set to a logic 1, inserts the 64-byte sequence TJ1DINS[64 --1][7:0], Page 0, 0x80--BF into the outgoing STS-3/STM-1 (AU-4) frame; a logic 0 inserts an all-zeros pattern (0x00 for all 64 bytes of the J1DINS bytes). The TJ1DINS[64--1][7:0] values are unchanged. Reset Default 0
Table 39. Register 62, 69: Transmit High-Speed Control Signals (R/W) Address Dec (Hex) 62 (0x3E) Bit 1 Name TS1INS Function Transmit S1 Insert (Control). Control bit, when set to a logic 1, inserts the value in TS1DINS[7:0], 0x45 into the outgoing S1 byte in the STS-3/STM-1 (AU-4) frame; a logic 0 inserts the default value. Reset Default 0
Table 40. Register 62, 66: Transmit High-Speed Control Signals (R/W) Address Dec (Hex) 62 (0x3E) Bit 0 Name TF1INS Function Transmit F1 Insert (Control). Control bit, when set to a logic 1, inserts the value in TF1DINS[7:0], 0x42 into the outgoing F1 byte in the STS-3/STM-1 (AU-4) frame; a logic 0 inserts the default value. Reset Default 0
Table 41. Registers 63--65: Trace/Growth Bytes (R/W) Address Dec (Hex) 63 (0x3F) Bit 7--0 Name TJ0DINS[7:0] Function Transmit J0 Data Insert Value. Register value is inserted into the STS-3/STM-1 (AU-4) output J0 byte. Transmit Z0-2 Data Insert Value. Register value is inserted into the STS-3/STM-1 (AU-4) output Z0-2 byte. Transmit Z0-3 Data Insert Value. Register value is inserted into the STS-3/STM-1 (AU-4) output Z0-3 byte. Reset Default 0x01
64 (0x40)
7--0
TZ02DINS[7:0]
0x02
65 (0x41)
7--0
TZ03DINS[7:0]
0x03
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Microprocessor Interface (continued)
Register Map (continued)
Table 42. Register 66: Transmit F1 Data Byte (R/W) Address Dec (Hex) 66 (0x42) Bit 7--0 Name TF1DINS[7:0] Function Transmit F1 Data Insert Value. See (addr 0x3E) for description. Reset Default 0x00
Table 43. Registers 67 and 68: K1 and K2 Insert Bytes (R/W) Address Dec (Hex) 67 (0x43) 68 (0x44) 67 (0x43) Bit 7--3 7--0 2--0 Name TAPSINS[12:8] TAPSINS[7:0] TK2INS[2:0] Function Transmit APS Data Insert Value. Register value is inserted into the STS-3/STM-1 (AU-4) output K1[7:0] and K2[7:3] bits. Transmit K2 Data Insert Value. Register value is inserted into the STS-3/STM-1 (AU-4) output K2[2:0] bits. Reset Default 0000000 000000 000
Table 44. Register 69: Transmit Sync Status Byte (R/W) Address Dec (Hex) 79 (0x45) Bit 7--0 Name TS1DINS [7:0] Function Transmit S1 Data Insert Value. See (addr 0x3E) for description. Reset Default 0x00
Table 45. Register 70: Path Signal Trace Byte (R/W) Address Dec (Hex) 70 (0x46) Bit 7--0 Name TC2DINS [7:0] Function Transmit C2 Data Insert Value. Register value is inserted into the STM-1(AU-4) output C2 byte. Reset Default 0x00
Table 46. Register 71: Path User Channel Byte (R/W) Address Dec (Hex) 71 (0x47) Bit 7--0 Name TF2DINS [7:0] Function Transmit F2 Data Insert Value. Register value is inserted into the STM-1(AU-4) output F2 byte. Reset Default 0x00
Table 47. Register 72: Path Growth Byte (R/W) Address Dec (Hex) 72 (0x48) Bit 7--0 Name TZ3DINS[7:0] Function Transmit Z3 Data Insert Value. Register value is inserted into the STM-1(AU-4) output Z3 byte. Reset Default 0x00
70
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface (continued)
Register Map (continued)
Table 48. Register 73: Tandem Connection Byte (R/W) Address Dec (Hex) 73 (0x49) Bit 7--0 Name TZ5DINS[7:0] Function Transmit Z5 Data Insert Value. Register value is inserted into the STM-1(AU-4) output Z5 byte. Reset Default 0x00
Table 49. Register 74: Transmit High-Speed Line RDI Insertion Inhibit Bits (R/W) Address Dec (Hex) 74 (0x4A) Bit 7 Name TLRDIINH Function Reset Default 1
74 (0x4A)
5
74 (0x4A) 74 (0x4A) 74 (0x4A) 74 (0x4A) 74 (0x4A)
4 3 2 1 0
Transmit RDI-L Inhibit Control. Control bit, when set to a logic 0, allows software to insert the TK2INS[2:0] byte, 0x43 into the outgoing K2[2:0] bits; otherwise, Line RDI 110 is inserted if the appropriate alarms are active. TRHSSF_LRDIINH Transmit Receive High-Speed Signal Fail L-RDI Inhibit. Control bits, when set to a logic 1, causes the associated failure not to contribute to the automatic insertion of RDI-L; otherwise, the associated alarm contributes to the generation of RDI-L. TRLAISMON_LRDIINH Transmit Receive Line AIS Path RDI Inhibit. Same as above. TRHSLOF_LRDIINH Transmit Receive High-Speed Loss-of-Frame Line RDI Inhibit. Same as above. TRHSOOF_LRDIINH Transmit Receive High-Speed Out-of-Frame Line RDI Inhibit. Same as above. TRHSLOS_LRDIINH Transmit Receive High-Speed Loss-of-Signal Line RDI Inhibit. Same as above. TRILOC_LRDIINH Transmit Receive Input Loss-of-Clock Line RDI Inhibit. Same as above.
0
0 1 0 0 0
Table 50. Register 75: Transmit High-Speed Path RDI Insertion Inhibit Bits (R/W) Address Dec (Hex) 75 (0x4B) Bit 7 Name TPRDIINS Function Transmit RDI-P Insert. Control bit, when set to a logic 1, allows software to insert P-RDI into the outgoing G1[3] bit, AU-4 mode only; otherwise, insert Path RDI under hardware control. Transmit Receive Loss-of-Pointer Path RDI Inhibit. Control bits, when set to a logic 1, causes the associated failure not to contribute to the automatic insertion of RDI-P; otherwise, the associated alarm contributes to the generation of RDI-P (port 1, AU-4 mode only). Transmit Receive Path AIS Path RDI Inhibit. Same as above. Reset Default 0
75 (0x4B)
6
TRLOP1_PRDIINH
0
75 (0x4B)
5
TRPAIS1_PRDIINH
0
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Data Sheet April 2001
Microprocessor Interface (continued)
Register Map (continued)
Table 50. Register 75: Transmit High-Speed Path RDI Insertion Inhibit Bits (R/W) (continued) Address Dec (Hex) 75 (0x4B) 75 (0x4B) 75 (0x4B) 75 (0x4B) 75 (0x4B) Bit 4 3 2 1 0 Name Function Reset Default 0 1 0 0 0
TRLAISMON_PRDIINH Transmit Receive Line AIS Path RDI Inhibit. Same as above. TRHSLOF_PRDIINH Transmit Receive High-Speed Loss-of-Frame Path RDI Inhibit. Same as above. TRHSOOF_PRDIINH Transmit Receive High-Speed Out-of-Frame Path RDI Inhibit. Same as above. TRHSLOS_PRDIINH Transmit Receive High-Speed Loss-ofSignal Path RDI Inhibit. Same as above. TRILOC_PRDIINH Transmit Receive Input Loss-of-Clock Path RDI Inhibit. Same as above.
Table 51. Register 76: Transmit High-Speed Error Insert Control Parameters (R/W) Address Dec (Hex) 76 (0x4C) Bit 4 Name THSB3ERRINS Function Transmit High-Speed B3 Error Insert. Control bit, when set to a logic 1, causes the output B3 byte in the outgoing STM-1 (AU-4) signal to be inverted. Transmit High-Speed B2 Error Insert. Control bit, when set to a logic 1, causes the output B2 bytes in the outgoing STS-3/STM-1 (AU-4) signal to be inverted. Transmit High-Speed B1 Error Insert. Control bit, when set to a logic 1, causes the output B1 byte in the outgoing STS-3/STM-1 (AU-4) signal to be inverted. Reset Default 0
76 (0x4C)
3--1
THSB2ERRINS[3--1]
000
76 (0x4C)
0
THSB1ERRINS
0
72
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface (continued)
Register Map (continued)
Table 52. Register 77: Transmit High-Speed Error Insert Control Parameters (R/W) Address Dec (Hex) 77 (0x4D) Bit 7 Name TPFEBEEINS Function Transmit Path FEBE Error Insert. Control bit, when set to a logic 1, causes a continuous Path FEBE error in the outgoing STM-1 (AU-4) signal; otherwise, a normal Path FEBE value is sent. Transmit Section FEBE Error Insert. Control bit, when set to a logic 1, causes a continuous Section FEBE error in the outgoing STS-3/STM-1 (AU-4) signal; otherwise, the normal Section FEBE value is sent. Transmit APS Babble Insert. Control bit, when set to a logic 1, causes an inconsistent APS byte (K1[7:0], K2[7:3]) to be inserted into the outgoing STS-3/STM-1 (AU-4) frame. Transmit Frame Error Insert Value. These bits specify the number of consecutive frames to be inserted with a frame error (A1A2). This register is used in conjunction with control bit TA1A2ERREN, 0x04. Reset Default 0
77 (0x4D)
6
TSFEBEEINS
0
77 (0x4D)
5
TAPSBABLEINS
0
77 (0x4D)
4--0
TA1A2ERRINS[4:0]
0x0
Table 53. Register 78: Transmit High-Speed Error Insert (R/W) Address Dec (Hex) 78 (0x4E) Bit 7--5 Name TH1H2CRUPEN[3--1] Function Transmit H1 H2 Corrupt Enable. Control bits, when set to a logic 1, cause the output H1 and H2 bytes of the STS-3/STM-1 (AU-4) signal to be corrupted on a per STS-1 basis. In the AU-4 mode, only control bit 1 is used. Transmit H1 H2 Corrupt or NDF. Control bit, when set to a logic 0, causes an invalid pointer to be inserted into the output H1 and H2 bytes; otherwise, a continuous NDF condition (1001) is sent. Transmit Test Pattern (223 - 1) or (215 - 1). Control bit, when set to a logic 0, causes a Q23 + Q17 +1 pattern to be inserted; otherwise, generate a Q15 + Q14 + 1 pattern. Transmit Test Generation Port Select. Control bits specify which TUG-3 the pseudorandom pattern is inserted into: 00 disable, 01 = TUG-3 #1, 10 = TUG-3 #2, 11 = TUG-3 #3. Reset Default 000
78 (0x4E)
4
TH1H2CRUPPorNDF
0
78 (0x4E)
2
TPAT23or15
0
78 (0x4E)
1--0
TSTGEN_PSEL[1:0]
00
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Data Sheet April 2001
Microprocessor Interface (continued)
Register Map (continued)
Table 54. Register 79: Receive/Transmit TOAC Control (R/W) Address Dec (Hex) 79 (0x4F) Bit 7 Name RTOAC_CLKINV Function Receive TOAC Clock Invert Control. Control bit, when set to a logic 1, forces the receive TOAC clock to be inverted leaving the device; otherwise, the clock is not inverted. Receive TOAC Sync A1 or Frame-End Align. Control bit, when set to a logic 0, forces the output 8 kHz frame sync signal to be aligned with the first bit of the frame; otherwise, align the output 8 kHz frame sync with the last bit of the previous frame. Receive TOAC Odd or Even Parity Insert. Control bit, when set to a logic 1, forces the output TOAC parity bit to be even; otherwise, the parity is odd. Receive TOAC Clock/Sync/Data Inhibit. Control bit, when set to a logic 1, forces the receive TOAC clock, sync, and data outputs to be placed in a highimpedance state. Transmit TOAC Clock Invert Control. Control bit, when set to a logic 1, forces the output clock to be inverted leaving the device; otherwise, the clock is not inverted. Transmit TOAC Sync A1 or Frame-End Align. Control bit, when set to a logic 0, forces the output 8 kHz frame sync signal to be aligned with the first bit of the frame; otherwise, align the output 8 kHz frame sync with the last bit of the previous frame. Transmit TOAC Odd or Even Parity Monitor. Control bit, when set to a logic 1, forces the input TOAC parity checker to check for odd parity; otherwise, even parity is checked on the transmit TOAC channel. Transmit TOAC Clock and Sync Inhibit. Control bit, when set to a logic 1, forces the transmit TOAC clock and sync to be placed in a high-impedance state. Reset Default 0
79 (0x4F)
6
RTOACS_A1orEND
0
79 (0x4F)
5
RTOAC_OEPINS
0
79 (0x4F)
4
RTOACINH
0
79 (0x4F)
3
TTOAC_CLKINV
0
79 (0x4F)
2
TTOACSA1orEND
0
79 (0x4F)
1
TTOAC_OEPMON
0
79 (0x4F)
0
TTOACINH
0
74
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface (continued)
Register Map (continued)
Table 55. Registers 80, 81: Transmit TOAC Control (R/W) Address Dec (Hex) 80 (0x50) Bit 7--6 Name TTOAC_E2[1:0] Function Transmit TOAC E2 Byte Control. Control bits, when set to a logic 00 or 11, cause the default value to be inserted into the E2 byte in the transmit STS3/STM-1 (AU-4) frame. Setting these control bits to a logic 01 causes the TTOAC value to be inserted into the E2 byte. Setting these control bits to a logic 10 causes the E2 value in the associated STS-1/ AU-3 to pass through unchanged. Transmit TOAC E1 Byte Control. Control bits, when set to a logic 00 or 11, cause the default value to be inserted into the E1 byte in the transmit STS3/STM-1 (AU-4) frame. Setting these control bits to a logic 01 causes the TTOAC value to be inserted into the E1 byte. Setting these control bits to a logic 10 causes the E1 value in the associated STS-1/ AU-3 to pass through unchanged. Transmit TOAC D4 to D12 Byte Control. Control bits, when set to a logic 00 or 11, cause the default value to be inserted into the D4 to D12 bytes in the transmit STS-3/STM-1 (AU-4) frame. Setting these control bits to a logic 01 causes the TTOAC values to be inserted into the D4 to D12 bytes, respectively. Setting these control bits to a logic 10 causes the D4 to D12 values in the associated STS-1/AU-3 to pass through unchanged. Transmit TOAC D1 to D12 Byte Control. Control bits, when set to a logic 00 or 11, cause the default value to be inserted into the D1 to D3 bytes in the transmit STS-3/STM-1 (AU-4) frame. Setting these control bits to a logic 01 causes the TTOAC values to be inserted into the D1 to D3 bytes, respectively. Setting these control bits to a logic 10 causes the D1 to D3 values in the associated STS-1/AU-3 to pass through unchanged. Reset Default 00
80 (0x50)
5--4
TTOAC_E1[1:0]
00
80 (0x50)
3--2
TTOAC_D4TO12[1:0]
00
80 (0x50)
1--0
TTOAC_D1TO3[1:0]
00
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Data Sheet April 2001
Microprocessor Interface (continued)
Register Map (continued)
Table 55. Registers 80, 81: Transmit TOAC Control (R/W) (continued) Address Dec (Hex) 81 (0x51) Bit 7--6 Name TTOAC_INS[1:0] Function Transmit TOAC Byte Control. Control bits, when set to a logic 00 or 11, cause the default value to be inserted into all overhead bytes without specific insert control bits in the transmit STS-3/STM-1 (AU-4) frame. Setting these control bits to a logic 01 causes the TTOAC value to be inserted into all overhead bytes without specific insert control bits. Setting these control bits to a logic 10 causes the associated STS-1/AU-3 values to pass through unchanged. Transmit TOAC Z2 Byte Control. Control bits, when set to a logic 00 or 11, cause the default value to be inserted into the Z2 byte in the transmit STS-3/STM-1 (AU-4) frame. Setting these control bits to a logic 01 causes the TTOAC value to be inserted into the Z2 byte. Setting these control bits to a logic 10 causes the Z2 value in the associated STS-1/AU-3 to pass through unchanged. Transmit TOAC Z1 Byte Control. Control bits, when set to a logic 00 or 11, cause the default value to be inserted into the Z1 byte in the transmit STS-3/STM-1 (AU-4) frame. Setting these control bits to a logic 01 causes the TTOAC value to be inserted into the Z1 byte. Setting these control bits to a logic 10 causes the Z1 value in the associated STS-1/AU-3 to pass through unchanged. Transmit TOAC F1 Byte Control. Control bits, when set to a logic 00 or 11, cause the default value to be inserted into the F1 byte in the transmit STS-3/STM-1 (AU-4) frame. Setting these control bits to a logic 01 causes the TTOAC value to be inserted into the F1 byte. Setting these control bits to a logic 10 causes the F1 value in the associated STS-1/AU-3 to pass through unchanged. Reset Default 00
81 (0x51)
5--4
TTOAC_Z2[1:0]
00
81 (0x51)
3--2
TTOAC_Z1[1:0]
00
81 (0x51)
1--0
TTOAC_F1[1:0]
00
76
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface (continued)
Register Map (continued)
Table 56. Register 83, 84: Transmit High-Speed STS-3/STM-1 Output Frame Offset (R/W) Address Dec (Hex) 83 (0x53) Bit 7--5 Name TLBITCNT[2:0] Function Transmit Load Bit Count. Allow the output STS-3/ STM-1 (AU-4) frame to have any relationship to the input J0 frame sync pulse (THSSJ0J1V1I (T/C)). The actual operation of these registers is listed below. Transmit Load Column Count. Same as above. Transmit Load STS1 Count. Same as above. Transmit Load Row Count. Same as above. Reset Default 000
83 (0x53) 84 (0x54) 83 (0x53) 84 (0x54)
3--0 7--4 4--3 2--0
TLCOLCNT[6:4] TLCOLCNT[3:0] TLSTS1CNT[1:0] TLROWCNT[3:0]
0000000 00 0000
THS SYNC/DATA Alignment Equations and Tables Equations for Sync Alignment: x = Desired Row y = Desired Column R, C, S, B, rmult, and cmult (See Table 57, A1-1 Alignment Parameters.) Equation 1. Equation 2. Equation 3. Equation 4. (((x * rmult) + (y * cmult))/cmult) * 1/90 = rowsub + colsub/90 rparm = R - rowsub cparm = C - colsub If (x = 8) then If (cparm = -2) then TLROWCNT = 8 TLCOLCNT = 88 Else if (cparm = -1) then TLROWCNT = 8 TLCOLCNT = 89 Else if (x | 8) then If (cparm = -2) then TLROWCNT = rparm - 1 TLCOLCNT = 88 Else if (cparm = -1) then TLROWCNT = rparm - 1 TLCOLCNT = 89
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Data Sheet April 2001
Microprocessor Interface (continued)
Register Map (continued)
Otherwise TLROWCNT = rparm TLCOLCNT = cparm Equation 5. If (THSCLKTYPE = BIT and THSPTYPE = BIT) TLBITCNT = (selected bit from BITCNT Alignment Table, Table 58 on page 80.) Otherwise TLBITCNT = B Equation 6. If (THSCLKTYPE = BIT and THSPTYPE = BIT and B 7) TLSTS1CNT = S - 1 (i.e., 0 2, 1 0, 2 1) If (STS #2) then TLCOLCNT = TLCOLCNT - 1 Else TLCOLCNT = TLCOLCNT If (y = 89 and STS #2 and TLROWCNT = 0) then TLROWCNT = 8 Else if (y = 89 and STS #2) then TLROWCNT = TLROWCNT - 1 Else TLROWCNT = TLROWCNT Otherwise TLSTS1CNT = S Examples 1. Align sync with D3, STS #1, THSCLKTYPE = BYTE, THSPTYPE = BYTE x = 2, y = 2 (from Table 57, A1-1 Alignment Parameters) (((2 * 270) + (2 * 3))/3) * 1/90 = 2 + 2/90 rparm = 8 - 2 = 6 cparm = 87 - 2 = 85 TLROWCNT = 6 TLCOLCNT = 86 TLBITCNT = 0 TLSTS1CNT = 2 (equation #1) (equation #2) (equation #3) (equation #4) (equation #4) (equation #5) (equation #6)
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface (continued)
Register Map (continued)
2. Align sync with row = 8, column = 89, STS #3 THSCLKTYPE = BYTE, THSPTYPE = BYTE x = 8, y = 89 (from Table 57, A1-1 Alignment Parameters) (((8 * 270) + (89 * 3))/3) * 1/90 = 8 + 89/90 rparm = 8 - 8 = 0 cparm = 87 - 89 = -2 TLROWCNT = 8 TLCOLCNT = 88 TLBITCNT = 0 TLSTS1CNT = 0 3. Align sync with row = 5, column = 89, STS #3 THSCLKTYPE = NIBBLE, THSPTYPE = BYTE x = 5, y = 89 (from Table 57, A1-1 Alignment Parameters) (((5 * 540) + (89 * 6))/6) * 1/90 = 5 + 89/90 rparm = 8 - 5 = 3 cparm = 88 - 89 = -1 TLROWCNT = 3 - 1 = 2 TLCOLCNT = 89 TLBITCNT = 0 TLSTS1CNT = 1 (equation #1) (equation #2) (equation #3) (equation #4) (equation #4) (equation #5) (equation #6) (equation #1) (equation #2) (equation #3) (equation #4) (equation #4) (equation #5) (equation #6)
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Data Sheet April 2001
Microprocessor Interface (continued)
Register Map (continued)
Table 57. A1-1 Alignment Parameters THSCLKTYPE BIT BIT BIT BIT BIT BIT BIT BIT BIT NIBBLE NIBBLE NIBBLE NIBBLE NIBBLE NIBBLE BYTE BYTE BYTE
* Aligns with MSN.
THSPTYPE BIT BIT BIT NIBBLE NIBBLE NIBBLE BYTE BYTE BYTE NIBBLE NIBBLE NIBBLE BYTE BYTE BYTE BYTE BYTE BYTE
STS # 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3
R 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
C 89 89 88 89 89 88 89 89 88 88 88 88 88 88 88 87 87 87
S 1 0 2 1 0 2 1 0 2 2 1 0 2 1 0 2 1 0
B 7 7 7 6* 6* 6* 6 6 6 1 1 1 1 1 1 0 0 0
rmult 2160 2160 2160 2160 2160 2160 2160 2160 2160 540 540 540 540 540 540 270 270 270
cmult 24 24 24 24 24 24 24 24 24 6 6 6 6 6 6 3 3 3
Table 58. BITCNT Alignment Table Valid for THSCLKTYPE = THSPTYPE only. MSB A1-1 BYTE BIT NIBBLE BYTE A1 Bit 7 B=7 A1 Bit 6 A1 Bit 5 B=0 B=1 (MSN) B = 1 A1 Bit 4 B=2 A1 Bit 3 B=3 B=0 LSB A1 Bit 2 A1 Bit 1 B=4 B=5 (LSN) B = 0 A1 Bit 0 B=6
80
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface (continued)
Register Map (continued)
Table 59. Register 85: Receive High/Low-Speed Port Control (R/W) Address Dec (Hex) 85 (0x55) Bit 7 Name THS2RHSLB Function Transmit High-Speed Receive High-Speed Loopback Control. Control bit, when set to a logic 1, causes the transmit output STS-3/STM-1 (AU-4) signal to be looped back to the receive input; otherwise, the loopback is disabled. Receive High-Speed Descramble Enable. Control bit, when set to a logic 1, causes the input STS-3/ STM-1 (AU-4) signal to be descrambled; otherwise, the signal is not descrambled. Receive Concatenation Mode. Control bit, when set to a logic 1, causes the input pointer interpreter to operate in concatenation mode. This mode is most likely used in the AU-4 mode; otherwise, three independent pointers are expected. Receive RDI Monitor Path Yellow or Enhanced Failure Code. Control bit, when set to a logic 0, causes the device to monitor path yellow in the incoming G1 byte bit 3; otherwise, the device monitors for an enhanced failure code in the G1 byte bits 3 down to 1. Receive High-Speed Verify Odd or Even Parity. Control bit when, set to a logic 0, causes odd parity to be verified in nibble/parallel mode per clock transfer on the STS-3/STM-1 (AU-4) input; otherwise, even parity is verified. Receive High-Speed Retime Edge Control. Control bit, when set to a logic 1, causes the STS-3/ STM-1 (AU-4) input data to be retimed on the positive edge; otherwise, the input STS-3/STM-1 (AU-4) input data is retimed on the falling edge of the input clock. Receive High-Speed Port Type. Control bits are used to control the type of output interface required: 00 = serial interface, 01 = nibble interface, 10 = byte-wide interface. Reset Default 0
85 (0x55)
6
RHSDSCR
0
85 (0x55)
5
RCONCATMODE
0
85 (0x55)
4
RRDI_MPYorEFC
0
85 (0x55)
3
RHSVOEPAR
0
85 (0x55)
2
RHSEDGE
0
85 (0x55)
1--0
RHSPTYPE[1:0]
00
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Data Sheet April 2001
Microprocessor Interface (continued)
Register Map (continued)
Table 60. Register 86: Receive J1 and Receive Low-Speed Port Select Control (R/W) Address Dec (Hex) 86 (0x56) Bit 7--6 Name J1PSELMON[1:0] Function J1 Port Select Monitor Control. Control bits are used to select which J1 byte will be monitored in the received STS-3/STM-1 (AU-4) signal: 00 = port 1, 01 = port 2, 10 = port 3, 11 = undefined operation. Receive Port Select Control. Control bits allow receive output selection: 00 or 11 = port 1 selected, 01 = port 2 selected, 10 = port 3 selected. Reset Default 00
86 (0x56)
5--4 3--2 1--0
RSEL[3--1][1:0]
10 01 00
Table 61. Register 87: STS-1/AU-3 Receive Control Bits (R/W) Address Dec (Hex) 87 (0x57) Bit 7--5 Name RLSSCR[3--1] Function Receive Low-Speed Scrambler Enable. Control bit, when set to a logic 1, causes the selected STS-1/AU-3 output signal to be scrambled; otherwise, the output signal is not scrambled. Receive High-Speed Port or CDR Clock and Data Select. Control bit, when set to a logic 0, causes the differential receive clock and data inputs (RHSSCLKIT/C, RHSSDATAIT/C) to be used in the device receive path; otherwise, the outputs of the CDR clock recovery block are used. Path AIS or LOP AIS Inhibit. Control bit, when set to a logic 0, causes state bits PAIS and LOP to contribute to the generation of Path AIS; otherwise, the state bits are inhibited from contributing to Path AIS generation. Transmit Low-Speed to Receive Low-Speed Loopback. Control bit, when set to a logic 1, causes the transmit STS-1/AU-3 input signals to be looped back to the receive STS-1/AU-3 outputs; otherwise, loopback is disabled. Receive Low-Speed Clock Invert Control. Control bit, when set to a logic 1, causes the output clock to be inverted; otherwise, the output STS-1/ AU-3 receive clock is not inverted. Receive Low-Speed Parity Odd or Even Generation. Control bit, when set to a logic 1, forces the output parity bit to be even; otherwise, the parity is odd. Reset Default 000
87 (0x57)
4
RHSPorCDRSEL
0
87 (0x57)
3
PAISLOP_AISINH
0
87 (0x57)
2
TLS2RLSLB
0
87 (0x57)
1
RLSCLKINV
0
87 (0x57)
0
RLSPAROEG
0
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface (continued)
Register Map (continued)
Table 62. Register 88: STS-1/AU-3 Receive Low-Speed AIS Inhibit Control Bits (R/W) Address Dec (Hex) 88 (0x58) Bit 7 Name RRLAISMON_AISINH Function Receive Line AIS Monitor AIS Inhibit. Control bits, when set to a logic 1, inhibit the associated alarm from causing AIS generation; otherwise, these allow the associated failure to cause AIS generation on all STS-1/AU-3 outputs. Receive High-Speed Loss-of-Signal AIS Inhibit. Same as above. Receive High-Speed Loss-of-Frame AIS Inhibit. Same as above. Receive High-Speed Out-of-Frame AIS Inhibit. Same as above. Receive Input Loss-of-Clock AIS Inhibit. Same as above. Reset Default 0
88 (0x58) 88 (0x58) 88 (0x58) 88 (0x58)
6 5 4 3
RRHSLOS_AISINH RRHSLOF_AISINH RRHSOOF_AISINH RRILOC_AISINH
0 1 0 0
Table 63. Registers 88, 89: STS-1/AU-3 Loss of Signal Detector (R/W) Address Dec (Hex) 88 (0x58) 89 (0x59) Bit 2--0 7--0 Name LOSDETCNT[10:8] LOSDETCNT[7:0] Function Loss-of-Signal Detection Count. Control bits are the number of consecutive all-zeros/-ones pattern detected to declare LOS state in the unscrambled STS-3/STM-1 (AU-4) input frame. A value of 0x02D equals 2.3 s while a value of 0x798 equals 100 s. Reset Default 0x02D = 2.3 s
Table 64. Register 90--95: Continuous N Times Detect (CNTD) Values (R/W) Address Dec (Hex) 90 (0x5A) Bit 7--4 Name CNTDF1[3:0] Function Continuous N Times Detect for F1 Byte. Register sets the number of CNTD occurrences of a consistent F1 value in the incoming STS-3/STM-1 (AU-4) frame. The valid range for this register is 0x3--0xF. Invalid values will be mapped to a value of 0x3. Continuous N Times Detect for J0Z0 Bytes. Register sets the number of CNTD occurrences of a consistent J0, Z0-2, and Z0-3 values in the incoming STS-3/STM-1 (AU-4) frame. The valid range for this register is 0x3--0xF. Invalid values will be mapped to a value of 0x3. Reset Default 0x3
90 (0x5A)
3--0
CNTDJ0Z0[3:0]
0x3
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Data Sheet April 2001
Microprocessor Interface (continued)
Register Map (continued)
Table 64. Register 90--95: Continuous N Times Detect (CNTD) Values (R/W) (continued) Address Dec (Hex) 91 (0x5B) Bit 7--4 Name CNTDAPS[3:0] Function Reset Default 0x3
91 (0x5B)
3--0
92 (0x5C)
7--4
92 (0x5C)
3--0
93 (0x5D)
7--4
93 (0x5D)
3--0
94 (0x5E)
7--4
Continuous N Times Detect for APS (K1, K2[7:3]) Byte. Register sets the number of CNTD occurrences of a consistent APS value in the incoming STS-3/STM-1 (AU-4) frame. The valid range for this register is 0x3--0xF. Invalid values will be mapped to a value of 0x3. CNTDK2[3:0] Continuous N Times Detect for K2[2:0] Byte. Register sets the number of CNTD occurrences of a consistent K2[2:0] value in the incoming STS-3/ STM-1 (AU-4) frame. The valid range for this register is 0x3--0xF. Invalid values will be mapped to a value of 0x3. CNTDAPSFRAME[3:0] Continuous N Times Detect for APS Frame Byte. Register sets the number of CNTD frames that an inconsistent APS value in the incoming STS-3/ STM-1 (AU-4) frame detects. This value is used in the APS Babble algorithm. The valid range for this register is 0x3--0xF. Invalid values will be mapped to a value of 0x3. CNTDS1[3:0] Continuous N Times Detect for S1 Byte. Register sets the number of CNTD occurrences of a consistent S1 value in the incoming STS-3/STM-1 (AU-4) frame. The valid range for this register is 0x3--0xF. Invalid values will be mapped to a value of 0x3. CNTDG1[3:0] Continuous N Times Detect for G1 Byte. Register sets the number of CNTD occurrences of a consistent G1 value in the incoming STS-3/STM-1 (AU-4) frame. The valid range for this register is 0x3--0xF. Invalid values will be mapped to a value of 0x3. CNTDC2[3:0] Continuous N Times Detect for C2 Byte. Register sets the number of CNTD occurrences of a consistent C2 value in the incoming STS-3/STM-1 (AU-4) frame. The valid range for this register is 0x3--0xF. Invalid values will be mapped to a value of 0x3. CNTDF2[3:0] Continuous N Times Detect for F2 Byte. Register sets the number of CNTD occurrences of a consistent F2 value in the incoming STS-3/STM-1 (AU-4) frame. The valid range for this register is 0x3--0xF. Invalid values will be mapped to a value of 0x3.
0x3
0xC
0x3
0x3
0x3
0x3
84
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface (continued)
Register Map (continued)
Table 64. Register 90--95: Continuous N Times Detect (CNTD) Values (R/W) (continued) Address Dec (Hex) 94 (0x5E) Bit 3--0 Name CNTDZ3[3:0] Function Continuous N Times Detect for Z3 Byte. Register sets the number of CNTD occurrences of a consistent Z3 value in the incoming STS-3/STM-1 (AU-4) frame. The valid range for this register is 0x3--0xF. Invalid values will be mapped to a value of 0x3. Continuous N Times Detect for Z5 Byte. Register sets the number of CNTD occurrences of a consistent Z5 value in the incoming STS-3/STM-1 (AU-4) frame. The valid range for this register is 0x3--0xF. Invalid values will be mapped to a value of 0x3. Reset Default 0x3
95 (0x5F)
3--0
CNTDZ5[3:0]
0x3
Table 65. Register 95: Continuous N Times Detect (CNTD) B1 Control Bit (R/W) Address Dec (Hex) 95 (0x5F) Bit 7 Name CNTDB1SEL Function Continuous N Times Detect B1 Select. Control bit, when set to a logic 1, causes the K2 byte CNTD monitors to be reset whenever a B1 error occurs; otherwise, B1 errors are ignored. Receive Loss-of-Clock Inhibit. Control bit, when set to a logic 1, inhibits the device receive path from using the transmit high-speed clock during an RILOC, 0x1B condition (AIS generation); otherwise, automatically switch to the transmit clock during a RILOC condition. Continuous N Times Detect Invalid Pointer and Invalid Concatenation Indication. Control bits are the number of consecutive conditions for invalid pointer and invalid concatenation indication (pointer interpretation). Valid values are the following: 00 = 8\D, 01 = 9\D, 10 = 10\D, and 11 = 8\D. Reset Default 0
95 (0x5F)
6
RLOCINH
0
95 (0x5F)
5--4
CNTCIP_ICI[1:0]
00
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Data Sheet April 2001
Microprocessor Interface (continued)
Register Map (continued)
Table 66. Register 96: Test Pattern Drop Control and Status Address Dec (Hex) 96 (0x60) Bit 7 Name RTSTDRP_OOS Function Receive Test Drop Out-of-Sync Indication (RO). State bit, when at a logic 1, indicates the test pattern is out of sync (OOS); a logic 0 indicates the test pattern monitor is in sync and able to count bit errors in the pseudorandom test pattern. Receive Test Drop Pattern Detect (223 - 1) or (215 - 1) (R/W). Control bit, when set to a logic 0, causes a Q23 + Q17 + 1 pattern to be monitored; otherwise, a Q15 + Q14 + 1 pattern is monitored. Receive Test Drop Port Select Control (R/W). Control bits specify which TUG-3 the pseudorandom pattern is to be monitored: 00 disable, 01 = TUG-3 #1, 10 = TUG-3 #2, 11 = TUG-3 #3. Reset Default 1
96 (0x60)
2
RPAT23or15
0
96 (0x60)
1--0
RTSTDRP_PSEL[1:0]
00
Table 67. Register 97: Test Pattern Drop Error Counter (RO) Address Dec (Hex) 97 (0x61) Bit 7--0 Name RTSTDRP_ECNT[7:0] Function Receive Test Drop Error Count. Value counts the number of errors received on the monitored pseudorandom signal. This counter will hold at its maximum value. Reset Default 0x00
Table 68. Register 98: Receive Low-Speed Overhead Control Bits (R/W) Address Dec (Hex) 98 (0x62) Bit 7--5 Name RA1A2ERRPEN[3--1] Function Receive A1A2 Error Insert Port Enables. Port into which framing errors will be injected. The number of consecutive frames that contain errors is controlled by RA1A2ERRINS[4:0] in the same register in which the action takes place when RA1A2ERREN, 0x04 transitions from a logic 0 to logic 1. Receive A1A2 Frame Error Insert. Same as above. Reset Default 000
98 (0x62)
4--0
RA1A2ERRINS[4:0]
0x1
86
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface (continued)
Register Map (continued)
Table 69. Register 99: Receive Low-Speed BIP Error Insert (R/W) Address Dec (Hex) 99 (0x63) Bit 5--3 Name RB2ERRINS[3--1] Function Receive B2 Error Insert Control. Control bit, when set to a logic 1, causes the respective B2 byte in the outgoing STS-1/AU-3 signal to be inverted. Receive B1 Error Insert Control. Control bit, when set to a logic 1, causes the respective B1 byte in the outgoing STS-1/AU-3 signal to be inverted. Reset Default 000
99 (0x63)
2--0
RB1ERRINS[3--1]
000
Table 70. Registers 100--102: Receive Low-Speed Overhead Control Bits (R/W) Address Dec (Hex) 100 (0x64) Bit 6 Name RH1H2CRUPPorNDF Function Reset Default 0
100 (0x64)
5--3
100 (0x64)
2--0
101 (0x65)
5--3
101 (0x65)
2--0
102 (0x66)
5--3
102 (0x66)
2--0
Receive H1 H2 Corrupt or NDF. Control bit, when set to a logic 0, causes an invalid pointer to be inserted into the output H1 and H2 bytes; otherwise, a continuous NDF condition (1001) is forced in the STS-1/AU-3 signal. RH1H2CRUPEN[3--1] Receive H1 H2 Corrupt Enable. Control bits, when set to a logic 1, causes the output H1 and H2 bytes of the STS-1/AU-3 signal to be corrupted as controlled by register bit RH1H2CRUPPorNDF in the same register. RF1INS[3--1] Receive F1 Data Insert. Control bits, when set to a logic 1, causes the RF1DINS[3--1][7:0], 0x6B--6D values to be inserted into the respective output F1 bytes in the STS-1/AU-3 signals; otherwise, insert the value set by the R_F1_PASS[3--1] control bit, 0x74. RSFEBEERRINS[3--1] Receive Section FEBE Error Insert. Control bit, when set to a logic 1, causes a Section FEBE (B2 Error value of 0x3) to be inserted into the STS-1/ AU-3 output signal; otherwise, an error is not inserted. RSFEBEINH[3--1] Receive Section FEBE Hardware Inhibit. Control bit, when set to a logic 1, inhibits the hardware insert of Section FEBE in the STS-1/AU-3 output signal; otherwise, the default value is inserted. RLAISINS[3--1] Receive Line AIS Insert. Control bit, when set to a logic 1, forces L-AIS to be inserted into the outgoing STS-1/AU-3 frame. RAPSBABLEINS[3--1] Receive APS Babble Insert. Control bit, when set to a logic 1, causes an inconsistent APS byte (K1[7:0], K2[7:3]) to be inserted into the outgoing STS-1/AU-3 frame.
000
000
000
000
000
000
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Microprocessor Interface (continued)
Register Map (continued)
Table 71. Register 103: Receive Low-Speed L-RDI Inhibit Control (R/W) Address Dec (Hex) 103 (0x67) Bit 6 Name
RTILOC_LRDIINH
Function
Reset Default 0
103 (0x67) 103 (0x67)
5--3 2--0
Receive Transmit Input Loss-of-Clock RDI-L Inhibit. Control bits, when set to a logic 1, inhibit the associated alarm from contributing to RDI-L generation per STS-1/AU-3 frame. RTLSLOF_LRDIINH[3--1] Receive Transmit Low-Speed Loss-of-Frame RDI-L Inhibit. Same as above. RTLSOOF_LRDIINH[3--1] Receive Transmit Low-Speed Out-of-Frame RDI-L Inhibit. Same as above.
111 000
Table 72. Registers 104--106: Receive Low-Speed C1 Byte (R/W) Address Dec (Hex) 104 (0x68) 105 (0x69) 106 (0x6A) Bit 7--0 Name RC1DINS[1--3][7:0] Function Receive C1 Data Insert. Register value is inserted into the respective STS-1/AU-3 output C1 byte. Reset Default 0x00
Table 73. Registers 107--109: Receive Low-Speed F1 Byte (R/W) Address Dec (Hex) 107 (0x6B) 108 (0x6C) 109 (0x6D) Bit 7--0 Name RF1DINS[1--3][7:0] Function Receive F1 Software Insert. Register value is inserted into the respective STS-1/AU-3 output F1 byte. Reset Default 0x00
Table 74. Registers 110--115: Receive Low-Speed K1, K2 Byte Insert (R/W) Address Dec (Hex) 110 (0x6E) 111 (0x6F) 112 (0x70) 113 (0x71) 114 (0x72) 115 (0x73) 110 (0x6E) 112 (0x70) 114 (0x72) Bit 7--3 7--0 7--3 7--0 7--3 7--0 2--0 Name RAPSINS1[12:8] RAPSINS1[7:0] RAPSINS2[12:8] RAPSINS2[7:0] RAPSINS3[12:8] RAPSINS3[7:0] RK2DINS[3--1][2:0] Function Receive APS Insert. Register value is inserted into the respective STS-1/AU-3 output K1 and K2[7:3] bytes. Reset Default 0x0000
Receive K2 Data Insert. Register value is inserted into the respective STS-1/AU-3 output K2[2:0] bits.
000
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Microprocessor Interface (continued)
Register Map (continued)
Table 75. Registers 116--118: Receive Low-Speed Pass Control (R/W) Address Dec (Hex) 116 (0x74) Bit 5--3 Name R_F1_PASS[3--1] Function Reset Default 000
116 (0x74)
2--0
117 (0x75)
5--3
117 (0x75)
2--0
118 (0x76)
5--3
118 (0x76)
2--0
Receive F1 Pass. Control bit, when set to a logic 1, allows the associated STS-3/STM-1 (AU-4) F1 byte to pass unchanged to the STS-1/AU-3 output signal; otherwise, the default value is inserted. R_E1_PASS[3--1] Receive E1 Pass. Control bit, when set to a logic 1, allows the associated STS-3/STM-1 (AU-4) E1 byte to pass unchanged to the STS-1/AU-3 output signal; otherwise, the default value is inserted. R_D4TOD12_PASS[3--1] Receive D4 to D12 Pass. Control bit, when set to a logic 1, allows the associated STS-3/STM-1 (AU-4) D4 to D12 bytes to pass unchanged to the STS-1/AU-3 output signal; otherwise, the default value is inserted. R_D1TOD3_PASS[3--1] Receive D1 to D3 Pass. Control bit, when set to a logic 1, allows the associated STS-3/ STM-1(AU-4) D1 to D3 bytes to pass unchanged to the STS-1/AU-3 output signal; otherwise, the default value is inserted. R_E2_PASS[3--1] Receive E2 Pass. Control bit, when set to a logic 1, allows the associated STS-3/STM-1 (AU-4) E2 byte to pass unchanged to the STS-1/AU-3 output signal; otherwise, the default value is inserted. R_S1_PASS[3--1] Receive S1 Pass. Control bit, when set to a logic 1, allows the associated STS-3/STM-1 (AU-4) S1 byte to pass unchanged to the STS-1/AU-3 output signal; otherwise, the default value is inserted.
000
000
000
000
000
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Data Sheet April 2001
Microprocessor Interface (continued)
Register Map (continued)
Table 76. Register 127: Page Control Register (R/W) Address Dec (Hex) 127 (0x7F) Bit 1--0 Name PAGE[1:0] Function Page Number. Control bits select the page accessed when an address greater than 128 is accessed: 00 = Page 0 (J1 Byte Insert/Monitor), 01 = Page 1 (Error Counters), 10 = Page 2 (BER Algorithm Parameters), 11 = Illegal Value. Reset Default 00
Table 77. Page 0 - Registers 128--191: J1 Insert Parameters (R/W) Address Dec (Hex) 128 (0x80)-- 191 (0xBF) Bit 7--0 Name TJ1DINS[64--1][7:0] Function Transmit J1 Data Insert. Registers allow a 64-byte sequence to be inserted into the J1 byte of the STM-1(AU-4) output signal. Reset Default 0x00
Table 78. Page 0 - Registers 192--255: J1 Monitor Bytes (RO) Address Dec (Hex)
192 (0xC0)-- 255 (0xFF)
Bit 7--0
Name RJ1MON[64--1][7:0]
Function Receive J1 Monitor Data. Registers capture a 64-byte sequence from the selected (J1PSELMON[1:0], 0x56) J1 byte of the STS-3/ STM-1 (AU-4) input signal.
Reset Default 0x00
Table 79. Page 1 - Registers 128--133: STS-1/AU-3 B1 BIP Error Counters (RO) Address Dec (Hex) 128 (0x80)-- 133 (0x85) Bit 7--0 Name TLSB1ECNT[1--3][15:8] TLSB1ECNT[1--3][7:0] Function Transmit Low-Speed B1 Error Count. These are the B1 BIP error rate counters. These counters can either count actual BIP errors or block errors (BITBLOCKCNT, 0x34). These counters hold at their maximum values and transfer their internal counts to a holding register when LATCH_CNT, 0x04 transitions from a logic 0 to 1. Reset Default 0x0000
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface (continued)
Register Map (continued)
Table 80. Page 1 - Registers 134--140: STS-1/AU-3 B2 BIP Error Counters (RO) Address Dec (Hex) 137 (0x89)-- 140 (0x8C) Bit 7--0 Name TLSB2ECNT[2--3][15:8] TLSB2ECNT[2--3][7:0] Function Reset Default
134 (0x86) 135 (0x87) 136 (0x88)
1--0 7--0 7--0
TLSB2ECNT[1][17:16] TLSB2ECNT[1][15:8] TLSB2ECNT[1][7:0]
0x0000 Transmit Low-Speed B2 Error Count Ports 2 and 3. These are the B2 BIP error rate counters. These counters can either count actual BIP errors or block errors (BITBLOCKCNT, 0x34). These counters hold at their maximum values and transfer their internal counts to a holding register when LATCH_CNT, 0x04 transitions from a logic 0 to 1. Transmit Low-Speed B2 Error Count Port 1. 0x00000 Same as above.
Table 81. Page 1 - Registers 141--142: STS-3/STM-1 (AU-4) B1 Error Count (RO) Address Dec (Hex) 141 (0x8D) 142 (0x8E) Bit 7--0 Name RHSB1ECNT[15:8] RHSB1ECNT[7:0] Function Receive High-Speed B1 Error Count. Counts the number of B1 errors in the received STS-3/ STM-1 (AU-4) frame. This counter can either count actual BIP errors or block errors (BITBLOCKCNT, 0x34). This counter holds at its maximum value and transfers its internal count to a holding register when LATCH_CNT, 0x04 transitions from a logic 0 to 1. Reset Default 0x0000
Table 82. Page 1 - Registers 143--145: STS-3/STM-1 (AU-4) B2 Error Count (RO) Address Dec (Hex) 143 (0x8F) 144 (0x90) 145 (0x91) Bit 1--0 7--0 7--0 Name RHSB2ECNT[17:16] RHSB2ECNT[15:8] RHSB2ECNT[7:0] Function Receive High-Speed B2 Error Count. Counts the number of B2 errors in the received STS-3/ STM-1 (AU-4) frame. This counter can either count actual BIP errors or block errors (BITBLOCKCNT, 0x34). This counter holds at its maximum value and transfers its internal count to a holding register when LATCH_CNT, 0x04 transitions from a logic 0 to 1. Reset Default 0x00000
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Microprocessor Interface (continued)
Register Map (continued)
Table 83. Page 1 - Registers 146--151: STS-3/STM-1 (AU-4) B3 Error Count (RO) Address Dec (Hex) 146 (0x92)-- 151 (0x97) Bit 7--0 Name Function Reset Default 0x0000
RHSB3ECNT[1--3][15:8] Receive High-Speed B3 Error Count. Counts RHSB3ECNT[1--3][7:0] the number of B3 errors in the receive STS-3/ STM-1 (AU-4) frame. Only counter value 1 is valid in AU-4 mode. This counter can either count actual BIP errors or block errors (BITBLOCKCNT, 0x34). This counter holds at its maximum value and transfers its internal count to a holding register when LATCH_CNT, 0x04 transitions from a logic 0 to 1.
Table 84. Page 1 - Registers 152--163: STS-3/STM-1 (AU-4) Pointer Increment/Decrement Counter (RO) Address Dec (Hex) 152 (0x98) 153 (0x99) 154 (0x9A) 155 (0x9B) 156 (0x9C) 157 (0x9D) 158 (0x9E) 159 (0x9F) 160 (0xA0) 161 (0xA1) 162 (0xA2) 163 (0xA3) Bit 2--0 7--0 2--0 7--0 2--0 7--0 2--0 7--0 2--0 7--0 2--0 7--0 Name RPTR_INC1[10:8] RPTR_INC1[7:0] RPTR_INC2[10:8] RPTR_INC2[7:0] RPTR_INC3[10:8] RPTR_INC3[7:0] RPTR_DEC1[10:8] RPTR_DEC1[7:0] RPTR_DEC2[10:8] RPTR_DEC2[7:0] RPTR_DEC3[10:8] RPTR_DEC3[7:0] Function Receive Pointer Increment Count. Counts the number of increments in the incoming pointer values. This counter holds at its maximum value and transfers its internal count to a holding register when LATCH_CNT, 0x04 transitions from a logic 0 to 1. Receive Pointer Decrement Count. Counts the number of decrements in the incoming pointer values. This counter holds at its maximum value and transfers its internal count to a holding register when LATCH_CNT, 0x04 transitions from a logic 0 to 1. Reset Default 0x000
0x000
Table 85. Page 1 - Registers 164--166: Receive High-Speed SFEBE Count (RO) Address Dec (Hex) 164 (0xA4) 165 (0xA5) 166 (0xA6) Bit 1--0 7--0 7--0 Name RSFEBECNT[17:16] RSFEBECNT[15:8] RSFEBECNT[7:0] Function Reset Default
Receive Section FEBE Count. Counts the num- 0x00000 ber of B2 errors received in the M1 byte of the receive STS-3/STM-1 (AU-4) frame. This counter can either count actual SFEBE errors or block errors (FEBEBITBLOCKCNT, 0x34). This counter holds at its maximum value and transfers its internal count to a holding register when LATCH_CNT, 0x04 transitions from a logic 0 to 1.
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface (continued)
Register Map (continued)
Table 86. Page 1 - Registers 167--172: Receive High-Speed Path FEBE Count (RO) Address Dec (Hex) 167 (0xA7)-- 172 (0xAC) Bit 7--0 Name Function Reset Default 0x0000
RPFEBECNT[1--3][15:8] Receive Path FEBE Count. Counts the number RPFEBECNT[1--3][7:0] of B3 errors received in the G1[7:4] bits of the received STS-3/STM-1 (AU-4) frame. This counter can either count actual PFEBE errors or block errors (FEBEBITBLOCKCNT, 0x34). This counter holds at its maximum value and transfers its internal count to a holding register when LATCH_CNT, 0x04 transitions from a logic 0 to 1.
Table 87. Page 2 - Register 131 (R/W) Address Dec (Hex) 131 (0x83) Bit 7 Name SDB1B2SEL Function Signal Degrade B1/B2 Error Count Select. Control bit, when set to a logic 0, causes the signal degrade bit error rate algorithm to use B1 errors; otherwise, B2 errors are used to calculate the error rate. Reset Default 0
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Microprocessor Interface (continued)
Register Map (continued)
Table 88. Page 2 - Registers 128--141 (R/W) Set parameters are used when RHSSD = 0, and the clear parameters are used when RHSSD = 1. Address Dec (Hex) 128 (0x80) 129 (0x81) 130 (0x82) 131 (0x83) 132 (0x84) Bit 2--0 7--0 7--0 3--0 7--0 Name SDNsSet[18:16] SDNsSet[15:8] SDNsSet[7:0] SDLSet[3:0] SDMSet[7:0] Function Signal Degrade Ns Set. Number of frames in a monitoring block for RHSSD, 0x1B. Signal Degrade L Set. Error threshold for determining if a monitoring block is bad. Signal Degrade M Set. Threshold of the number of bad monitoring blocks in an observation interval. If the number of bad blocks is above this threshold, then RHSSD, 0x1B is set. Signal Degrade B Set. Number of monitoring blocks. Signal Degrade Ns Clear. Number of frames in a monitoring block for RHSSD, 0x1B. Signal Degrade L Clear. Error threshold for determining if a monitoring block is bad. Signal Degrade M Clear. Threshold of the number of good monitoring blocks in an observation interval. If the number of good blocks is above this threshold, then RHSSD, 0x1B is cleared. Signal Degrade B Clear. Number of monitoring blocks. Reset Default 0x00000
0x0 0x00
133 (0x85) 134 (0x86) 135 (0x87) 136 (0x88) 137 (0x89) 138 (0x8A) 139 (0x8B)
7--0 2--0 7--0 7--0 3--0 7--0
SDBSet[15:8] SDBSet[7:0] SDNsClear[18:16] SDNsClear[15:8] SDNsClear[7:0] SDLClear[3:0] SDMClear[7:0]
0x0000 0x00000
0x0 0x00
140 (0x8C) 141 (0x8D)
7--0
SDBClear[15:8] SDBClear[7:0]
0x0000
Note: The thresholds written by the control system shall be one less than the desired number, except for the SDLSet/Clear[3:0] parameter. Timing requirements: When SDSET (0x04) is set to a 1, the device sets RHSSD = 1, clears all remaining internal variables and counters of the RHSSD algorithm, and initializes the algorithm to enable recovery declaration. When SDCLEAR (0x04) is set to a 1, the device sets RHSSD = 0, clears all remaining internal variables and counters of the RHSSD algorithm and initializes the algorithm to enable failure declaration. If SDSET OR SDCLEAR is cleared to 0, do nothing. If SDSET AND SDCLEAR are simultaneously set to 1, do nothing. BER algorithm: while (SDL = 0) then disable algorithm and set RHSSD, RHSSDD = 0.
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface (continued)
Register Map (continued)
If (SDB1B2SEL = 0) then use B1 BIP errors in BERR algorithm else use B2 BIP errors in BERR algorithm end if; if (NEWFRAME) then { INCR (FRAMECNTR) BIPERR = BIPERR + NEWERR if (BIPERR > SDL) then BIPERR = SDL if (FRAMECNTR = SDNs) then -- Number of frames in monitoring block { RESET (FRAMECNTR) if (BIPERR SDL) then BLOCK = 1 else BLOCK = 0 INCR (BTOTCNTR) RESET (BIPERR) If (RHSSD = 0) then { if (BLOCK = 1) then { INCR (BMONCNTR) if (BMONCNTR SDM) then { RHSSD = 1; RHSSDD = 1 RESET (BMONCNTR); RESET (BTOTCNTR) } } else if (BTOTCNTR = SDB) then } RESET (BMONCNTR); RESET (BTOTCNTR) } } /* indicates good monitoring period. */ /* indicates bad monitoring period. */
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Microprocessor Interface (continued)
Register Map (continued)
if (RHSSD = 1) then { if (BLOCK = 0) then { INCR (BMONCNTR) if (BMONCNTR SDM) then { RHSSD = 0; RHSSDD = 1 RESET (BMONCNTR); RESET (BTOTCNTR) } } else if (BTOTCNTR = SDB) then { RESET (BMONCNTR); RESET (BTOTCNTR) } } } } WHERE: NEWFRAME = checks for frame sync signal (internal) to reinitiate BER calculation. FRAMECNTR = count of number of frames since the start of the latest monitoring period. BIPERR = number of composite B1 or B2 errors so far in latest monitoring period. NEWERR = number of composite B1 or B2 errors calculated in latest frame. BLOCK = indication of good (0) or bad (1) latest monitoring period. BTOTCNTR = count of current total number of monitoring periods (good or bad) in latest observation interval. BMONCNTR = count of current number of: bad monitoring periods in latest observation interval if RHSSD = 0, good monitoring periods in latest observation interval if RHSSD = 1.
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface (continued)
Register Map (continued)
Table 89. Page 2 - Register 145 (R/W) Address Dec (Hex) 145 (0x91) Bit 7 Name SFB1B2SEL Function Signal Fail B1/B2 Error Count Select. Control bit, when set to a logic 0, causes the signal fail bit error rate algorithm to use B1 errors; otherwise, B2 errors are used to calculate the error rate. Reset Default 0
Table 90. Page 2 - Registers 142--155 (R/W) The set parameters are used when RHSSF = 0, and the clear parameters are used when RHSSF = 1. Address Dec (Hex) 142 (0x8E) 143 (0x8F) 144 (0x90) 145 (0x91) 146 (0x92) Bit 2--0 7--0 7--0 3--0 7--0 Name SFNsSet[18:16] SFNsSet[15:8] SFNsSet[7:0] SFLSet[3:0] SFMSet[7:0] Function Reset Default
Signal Fail Ns Set. Number of frames in a monitor- 0x00000 ing block for RHSSF, 0x1B. Signal Fail L Set. Error threshold for determining if a monitoring block is bad. Signal Fail M Set. Threshold of the number of bad monitoring blocks in an observation interval. If the number of bad blocks is above this threshold, then RHSSF, 0x1B is set. Signal Fail B Set. Number of monitoring blocks. Signal Fail Ns Clear. Number of frames in a monitoring block for RHSSF, 0x1B. Signal Fail L Clear. Error threshold for determining if a monitoring block is bad. Signal Fail M Clear. Threshold of the number of good monitoring blocks in an observation interval. If the number of good blocks is above this threshold, then RHSSF, 0x1B is cleared. Signal Fail B Clear. Number of monitoring blocks. 0x0 0x00
147 (0x93) 148 (0x94) 150 (0x96) 151 (0x97) 152 (0x98) 152 (0x98) 153 (0x99)
7--0 2--0 7--0 7--0 3--0 7--0
SFBSet[15:8] SFBSet[7:0] SFNsClear[18:16] SFNsClear[15:8] SFNsClear[7:0] SFLClear[3:0] SFMClear[7:0]
0x0000 0x00000
0x0 0x00
154 (0x9A) 155 (0x9B)
7--0
SFBClear[15:8] SFBClear[7:0]
0x0000
Note: The thresholds written by the control system shall be one less than the desired number, except for the SFLSet/Clear[3:0] parameter.
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Data Sheet April 2001
Microprocessor Interface (continued)
Register Map (continued)
Timing requirements: When SFSET is set to a 1, the device sets RHSSF = 1, clears all remaining internal variables and counters of the RHSSF algorithm and initializes the algorithm to enable recovery declaration. When SFCLEAR is set to a 1, set RHSSF = 0, clears all remaining internal variables and counters of the RHSSF algorithm, and initializes the algorithm to enable failure declaration. If SFSET OR SFCLEAR is cleared to a 0, do nothing. If SFSET AND SFCLEAR are simultaneously set to a 1, do nothing. BER algorithm: While (SFL = 0) then disable algorithm and set RHSSF, RHSSFD = 0.
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface (continued)
Register Map (continued)
if (SFB1B2SEL = 0) then use B1 BIP errors in BER algorithm else use B2 BIP errors. if (NEWFRAME) then { INCR (FRAMECNTR) BIPERR = BIPERR + NEWERR if (BIPERR > SFL) then BIPERR = SFL if (FRAMECNTR = SFNs) then { RESET (FRAMECNTR) if (BIPERR SFL) then BLOCK = 1 else BLOCK = 0 INCR (BTOTCNTR) RESET (BIPERR) If (RHSSF = 0) then { if (BLOCK = 1) then { INCR (BMONCNTR) if (BMONCNTR SFM) then { RHSSF = 1; RHSSFD = 1 RESET (BMONCNTR); RESET (BTOTCNTR) } } else if (BTOTCNTR = SFB3) then } RESET (BMONCNTR); RESET (BTOTCNTR) } } /* indicates good monitoring period. */ /* indicates bad monitoring period. */
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Data Sheet April 2001
Microprocessor Interface (continued)
Register Map (continued)
if (RHSSF = 1) then { if (BLOCK = 0) then { INCR (BMONCNTR) if (BMONCNTR MSF) then { RHSSF = 0; RHSSFD = 1 RESET (BMONCNTR); RESET (BTOTCNTR) } } else if (BTOTCNTR = BSF) then { RESET (BMONCNTR); RESET (BTOTCNTR) } } } } Where: NEWFRAME = checks for frame sync signal (internal) to reinitiate BER calculation. FRAMECNTR = count of number of frames since the start of the latest monitoring period. BIPERR = number of composite B2 errors so far in latest monitoring period. NEWERR = number of composite B2 errors calculated in latest frame. BLOCK = indication of good(0) or bad(1) latest monitoring period. BTOTCNTR = count of current total number of monitoring periods (good or bad) in latest observation interval. BMONCNTR = count of current number of: bad monitoring periods in latest observation interval if RHSSF = 0, good monitoring periods in latest observation interval if RHSSF = 1.
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Microprocessor Interface (continued)
I/O Timing
The I/O timing specifications for the microprocessor interface are given in Table 92. The microprocessor interface pins use CMOS I/O levels. All outputs, except the address/data bus AD[7:0], are rated for a capacitive load of 50 pF. The AD[7:0] outputs are rated for a 100 pF load. The minimum read and write cycle time is 200 ns for all device configurations. Table 91. Microprocessor Interface I/O Timing Specifications Symbol Configuration Parameter Setup (ns) (Min)
5 -- 0 25 -- -- -- -- -- -- -- -- 7 20 7.5 -- -- -- 15 -- 30 -- -- -- -- 35 -- 25 -- -- -- -- -- --
Hold (ns) (Min)
-- 10 -- -- -- -- -- -- -- -- 55 25 -- -- -- -- -- 30 -- 10 -- -- -- -- -- -- -- -- -- -- 25 150 100 100
Delay (ns) (Max)
-- -- -- -- 20 24 44 -- 15 15 -- -- -- -- -- 20 7.5 -- -- -- -- 90 75 15 25 -- 16 -- 73 22 -- -- -- --
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 t34
MODES 1 and 2
Address Valid to AS Asserted (Read, Write)
AS Asserted to Address Invalid (Read, Write) AS Asserted to DS Asserted
R/W High (Read) to DS Asserted
DS Asserted (Read, Write) to DTACK Asserted DTACK Asserted to Data Valid (Read) DS Asserted (Read) to Data Valid DS Negated (Read, Write) to AS Negated DS Negated (Read) to Data Invalid DS Negated (Read) to DTACK Negated AS (Read, Write) Asserted Width DS (Read) Asserted Width AS Asserted to R/W Low (Write)
R/W Low (Write) to DS Asserted Data Valid to DS Asserted (Write)
DS Negated to DTACK Negated (Write) DS Negated to Data Invalid (Write) DS (Write) Asserted Width
MODES 3 and 4
Address Valid to ALE Asserted Low (Read, Write) ALE Asserted Low (Read, Write) to Address Invalid ALE Asserted Low to RD Asserted (Read)
RD Asserted (Read) to Data Valid RD Asserted (Read) to RDY Asserted RD Negated to Data Invalid (Read) RD Negated to RDY Negated (Read)
ALE Asserted Low to WR Asserted (Write)
CS Asserted to RDY Asserted Low
Data Valid to WR Asserted (Write)
WR Asserted (Write) to RDY Asserted WR Negated to RDY Negated (Write) WR Negated to Data Invalid
ALE Asserted (Read, Write) Width
RD Asserted (Read) Width WR Asserted (Write) Width
The read and write timing diagrams for all four microprocessor interface modes are shown in Figures 7--14. Agere Systems Inc. 101
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Data Sheet April 2001
Microprocessor Interface (continued)
I/O Timing (continued)
MINIMUM READ CYCLE CS
t11 AS t2 t1 A[7:0] VALID ADDRESS t8
R/W t4 t3 DS t6 t5 DTACK t7 AD[7:0] VALID DATA t9 t10 t12
5-3685(F).br.4
Figure 7. MODE 1--Read Cycle Timing (MPMODE = 0, MPMUX = 0)
MINIMUM WRITE CYCLE CS t11 AS t2 t1 A[7:0] t13 t14 R/W VALID ADDRESS t8
t18 DS t5 DTACK t15 AD[7:0] VALID DATA
5-3686(F).br.5
t16
t17
Figure 8. MODE 1--Write Cycle Timing (MPMODE = 0, MPMUX = 0) 102 Agere Systems Inc.
Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface (continued)
I/O Timing (continued)
MINIMUM READ CYCLE CS t11 AS t8 R/W t4 t3 DS t7 t5 t6 DTACK t2 t1 AD[7:0] VALID DATA VALID ADDRESS VALID DATA t9 VALID ADDRESS t10 t12
5-3687(F)r.12
Figure 9. MODE 2--Read Cycle Timing (MPMODE = 0, MPMUX = 1)
MINIMUM WRITE CYCLE CS t11 AS t13 t14 R/W t18 DS t5 DTACK t2 t1 AD[7:0] VALID DATA VALID ADDRESS t15 VALID DATA t17 VALID ADDRESS t16 t8
5-3688(F)r.12
Figure 10. MODE 2--Write Cycle Timing (MPMODE = 0, MPMUX = 1)
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Data Sheet April 2001
Microprocessor Interface (continued)
I/O Timing (continued)
MINIMUM READ CYCLE CS t32 ALE* t19 t20 A[7:0] t21 t33 RD t22 AD[7:0] t27 RDY
5-3689(F).b
VALID ADDRESS
t24 VALID DATA t23 t25
* If ALE is not used, the A[7:0] address bus must be valid t21 ns before RD is asserted low, and stay valid t25 ns after RD rises.
Figure 11. MODE 3--Read Cycle Timing (MPMODE = 1, MPMUX = 0)
MINIMUM WRITE CYCLE CS t32 ALE* t19 t20 A[7:0] t26 t34 WR t28 AD[7:0] t27 RDY t29 VALID DATA t30 t31 VALID ADDRESS
* If ALE is not used, the A[7:0] address bus must be valid t26 ns before WR is asserted low, and stay valid t31 ns after WR rises.
5-3690(F).dr.4
Figure 12. MODE 3--Write Cycle Timing (MPMODE = 1, MPMUX = 0) 104 Agere Systems Inc.
Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Microprocessor Interface (continued)
I/O Timing (continued)
MINIMUM READ CYCLE CS t32 ALE t21 t33 RD t19 AD[7:0] VALID DATA t27 RDY t20 VALID ADDRESS t23 t22 VALID DATA t25 t24 VALID ADDRESS
5-3691(F)r.12
Figure 13. MODE 4--Read Cycle Timing (MPMODE = 1, MPMUX = 1)
MINIMUM WRITE CYCLE CS t32 ALE t26 WR t19 t20 AD[7:0] VALID DATA t27 RDY
5-3692(F)r.13
t34
t28 VALID DATA t29
t31 VALID ADDRESS t30
VALID ADDRESS
Figure 14. MODE 4--Write Cycle Timing (MPMODE = 1, MPMUX = 1)
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Data Sheet April 2001
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter dc Supply Voltage Range Power Dissipation Storage Temperature Range Ambient Operating Temperature Range Maximum Voltage (digital input pins) with Respect to REF5VTOL Minimum Voltage (digital input pins) with Respect to VSS Symbol VDD PD Tstg TA -- -- Min -0.5 -- -65 -40 -- -0.3 Max 4.6 -- 125 85 0.3 -- Unit V mW C C V V
Handling Precautions
Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Agere employs a human-body model (HBM) and charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used in the defined model. No industry-wide standard has been adopted for the CDM. However, a standard HBM (resistance = 1500 W, capacitance = 100 pF) is widely used and, therefore, can be used for comparison purposes. The HBM ESD threshold presented here was obtained by using these circuit parameters: Device TMUX03155 Voltage 2500 V
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Operating Conditions
The following tables list the voltages required for proper operation of the TMUX03155 device, along with their tolerances. Table 92. Recommended Operating Conditions Parameter Power Ground Input Voltage, High Input Voltage, Low 5 V Tolerant Reference Voltage1 3.3 V Tolerant Reference Voltage* 1.0 V: LVDS Reference2 1.4 V: LVDS Reference Symbol VDD VSS VIH VIL REF5VTOL LVDS_REF10 LVDS_REF14 Min 3.14 -- -- -- 4.75 3.14 -- -- Typ 3.3 0.0 VDD - 1.0 VSS 5.0 3.3 1.0 1.4 Max 3.47 -- REF5VTOL 1.0 5.25 3.47 -- -- Unit V V V V V V V V
1. This input should be connected to 5.0 V when the device interfaces with 5 V and 3.3 V signals, or 3.3 V when the device only interfaces with 3.3 V signals. 2. Use internal reference voltages if LVDS_REFSEL = 0 or external voltage tolerance is > 5%.
Table 93. Power Measurements (VDD = 3.3 V, 23 C) Device Mode STS-3/AU-4 to/from STS-1/AU-3 STS-1/AU-3 to STS-3/AU-4 Loopback (THS2RHSLB = 1) Standby Power 600 6101 570 Unit mW mW
550
mW
1. 85 C ambient temperature (not case temperature).
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Data Sheet April 2001
Electrical Characteristics
Table 94. Logic Interface Characteristics Parameter Input Leakage Output Current*: Low High Output Voltage: Low High Input Capacitance Symbol IL IOL IOH VOL VOH CI -- -- Test Conditions -- -- Min -- -- -- VSS VDD - 0.5 -- Max 1.0 2 2 0.5 REF5VTOL 1.5 Unit A mA mA V V pF
* All outputs are 2 mA except TLSSPEO, TLSJ0J1VV1TIMEO, TLSV1TIMEO, THSSSYNCO, THSDATA[7:0]O, THSPARO, RLSJ0TIMEO, RLSDATA[7:0]O, and RLSPARO which are 4 mA buffers.
The input specification for the remaining (nonbalanced) inputs are specified in Figure 15. See Operational Timing on page 110
VIH
VIL
tF tR
5-6032(F)r.2
Figure 15. Single-Ended Input Specification
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Electrical Characteristics (continued)
Table 95. LVDS Interface Characteristics 3.3 V 5% VDD, 0--125 C, slow--fast process. Parameter Input Voltage Range, VIA or VIB Input Differential Threshold Input Differential Hysteresis Receiver Differential Input Impedance Output Voltage: Low (VOA or VOB) High (VOA or VOB) Output Differential Voltage Output Offset Voltage Output Impedance, Single Ended RO Mismatch Between A and B Change in Differential Voltage Between Complementary States Change in Output Offset Voltage Between Complementary States Output Current Output Current Symbol VI Test Conditions Min 0.0 -100 -- 80 Typ 1.2 -- -- 100 Max 2.4 100 --* 120 Unit V mV mV Input Buffer Parameters |VGPD| < 925 mV, dc--1 MHz |VGPD| < 925 mV, VIDTH 311 MHz (+VIDTH) - (-VIDTH) VHYST RIN With build-in termination, center-tapped Output Buffer Parameters VOL VOH |VOD| VOS RO RO |VOD| VOS ISA, ISB ISAB RLOAD = 100 1% RLOAD = 100 1% RLOAD = 100 1% RLOAD = 100 1% VCM = 1.0 V and 1.4 V VCM = 1.0 V and 1.4 V RLOAD = 100 1% RLOAD = 100 1% Driver shorted to VSS Drivers shorted together
-- 0.925 0.25 1.125 40 -- -- -- -- --
-- -- -- 50 -- -- -- -- --
1.475 -- 0.40 1.275 60 10 25 25 24 12
V V V V % mV mV mA mA
* Buffer will not produce output transition when input is open-circuited.
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Data Sheet April 2001
Timing Characteristics
Operational Timing
The operational timing parameters can be grouped separately for clocks, inputs, and outputs. Table 96 lists the input clock specifications for this device. The rise and fall times refer to the transition times from 10% to 90% of full swing. (For definitions of the signal names, see the pin descriptions in Table 1, pages 10--15.) Table 96. Input Clock Specifications Symbol fOP Parameter Operating Frequency Signal Name THSSCLKIT/C1 THSCLKI RHSSCLKIT/C* RHSCLK TCLK THSSCLKIT/C* THSCLKI RHSSCLKIT/C* RHSCLK TCLK THSSCLKIT/C* THSCLKI RHSSCLKIT/C* RHSCLK TCLK THSSCLKIT/C* THSCLKI RHSSCLKIT/C* RHSCLK TCLK Min -- -- -- -- -- 2.5 11.0/22.0 2.5 11.0/22.0 30 1.5 3.5 1.5 3.5 15 1.5 3.5 1.5 3.5 15 Max 155.52 + 0.4% 38.88/19.44 + 1% 155.52 + 0.5% 38.88/19.44 + 1% 0.5--12 + 1% -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tCLKH
Clock Pulse High Time
tR
Rise Time
tF
Fall Time
1. When the true and complement inputs are floating, the input buffer will not oscillate.
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Timing Characteristics (continued)
Operational Timing (continued)
The following table lists input setup and hold times and reference clocks. (See Figure 17, Interface Data Timing, on page 115.) Table 97. Input Timing Specifications Input Name Reference CLK Setup Time (tSU) Min Transmit Signals THSSJ0J1V1IT/C* THSJ0J1V1I TLSDATA[7:0]I TLSPARI TTOACDATAI RHSSDATAIT/C RHSPARI RHSLOSEXTI TDI TMS TRST SCAN_EN TEST_MODE MODE [1:0] RESET ICT
1
Hold Time (tH) Min 0.0 0.0 Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Unit
Max --
THSSCLKIT/C THSCLKI TLSCLKO TLSCLKO TTOACCLKO RHSSCLKIT/C RHSCLKI RHSCLKI NA TCLK TCLK NA NA NA NA NA NA
2.0 2.0 5.0 5.0 Transmit TOAC 10.0 Receive Signals 2.0 5.0 5.0 ASYNC JTAG and SCAN 15 15 ASYNC ASYNC ASYNC Miscellaneous ASYNC ASYNC ASYNC
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Transmit Low-Speed Signals -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.0 0.0 10.0 0.0 0.0 0.0 ASYNC 15 15 ASYNC ASYNC ASYNC ASYNC ASYNC ASYNC
RHSDATA[7:0]I
1. When the true and complement inputs are floating, the input buffer will not oscillate.
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THSCLKTYPE = BIT CLOCK (155.52 MHz) 19440 CLOCK CYCLES/FRAME (125 s) 500 s J1 125 s V1* J0 J0 J0 J0 J1 V1* 125 s J1 125 s J1 125 s J1 1 23 19392 1 19416 23 1 23 19416 1 23 19416 1 23 1 23 1 THSCLKTYPE = NIBBLE CLOCK (38.88 MHz) 4860 CLOCK CYCLES/FRAME (125 s) 500 s J1 125 s V1* J0 J0 J0 125 s J1 125 s J1 125 s J1 J0 J1 V1* 1 5 4848 1 5 4854 1 5 4854 1 5 4854 1 5 1 5 1 THSCLKTYPE = BYTE CLOCK (19.44 MHz) 2430 CLOCK CYCLES/FRAME (125 s) 500 s
SUPERFRAME
FRAME
MSB
J0
THSSJ0J1V1IT
Operational Timing (continued)
Timing Characteristics (continued)
CLOCK CYCLES
1
23
SUPERFRAME
FRAME
MSN
J0
THSJ0J1V1I
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
CLOCK CYCLES
1
5
The following diagram defines the signal structure of the input signal THSJ0J1V1I.
SUPERFRAME
Figure 16. THSJ0J1V1I Signal Structure Definition
J1 125 s V1* J0 J0 125 s J1 125 s J1 J0 125 s J1 J0 J1 V1* 1 2 2424 1 2 2427 1 2 2427 1 2 2427 1 2 1 2 1
FRAME
MSB
J0
THSJ0J1V1I
CLOCK CYCLES
1
2
* Optional. MSB = most significant bit, most significant byte, respectively; MSN = most significant nibble.
5-6253 (F)r.2
Data Sheet April 2001
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Timing Characteristics (continued)
Operational Timing (continued)
The output clock specifications are shown in Table 98. Table 98. Output Clock Specifications Signal Name Reference CLK1 Frequency2 Test Conditions Rise Time tR Min TLSCLKO THSSCLKO THSCLKO THSSCLKIT/C or 19.44 MHz 5% CL = 50 pF THSCLKI THSSCLKIT/C 155.52 MHz 3% CL = 15 pF -- -- -- Max 3.5 1.5 3.5 Min -- -- -- Fall Time tF Max 3.5 1.5 3.5 ns ns ns Unit
THSSCLKIT/C or 38.88 MHz 5% CL = 15 pF THSCLKI or 19.44 MHz 5%
TTOACCLKO THSSCLKIT/C or 5.184 MHz 5% CL = 15 pF THSCLKI RLSCLKO RHSSCLKIT/C or 19.44 MHz 5% CL = 50 pF RHSCLKI or Internal CDR Clock
-- --
3.5 3.5
-- --
3.5 3.5
ns ns
RTOACCLKO RHSSCLKIT/C or 5.184 MHz 5% CL = 15 pF RHSCLKI or Internal CDR Clock
1. The specifications for the table are with all loopbacks disabled. 2. The frequency percentages refer to the respective duty cycles.
--
3.5
--
3.5
ns
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Data Sheet April 2001
Timing Characteristics (continued)
Operational Timing (continued)
The following table lists the propagation delay specifications for the outputs. (See Figure 17, Interface Data Timing, on page 115. ) Table 99. Output Timing Specifications Output Name Reference CLK Test Conditions Propagation Delay tPD Min Transmit Low-Speed Signals TLSSPEO TLSJ0J1V1TIMEO TLSV1TIMEO THSSCLKIT/C THSSSYNCOT/C* THSSDATAOT/C* THSSYNCO THSDATA[7:0]O THSPARO THSCLKI TTOACSYNCO RLSJ0TIMEO RLSDATA[7:0]O RLSPARO RTOACSYNCO RTOACDATAO INTN TDO TLSCLKO TLSCLKO TLSCLKO THSSCLKOT/C THSSCLKOT/C THSSCLKOT/C THSCLKO THSCLKO THSCLKO THSCLKO TTOACCLKO RLSCLKO RLSCLKO RLSCLKO RTOACCLKO RTOACCLKO ASYNC TCLK CL = 50 pF CL = 50 pF CL = 50 pF CL = 15 pF CL = 15 pF CL = 15 pF CL = 15 pF CL = 15 pF CL = 15 pF CL = 15 pF Transmit TOAC Signal CL = 15 pF CL = 50 pF CL = 50 pF CL = 50 pF Receive TOAC Signals CL = 15 pF CL = 15 pF NA JTAG and SCAN CL = 25 pF 3.0 20.0 ns
* Propagation delay skew, tPLH--tPHL, is 200 ps.
Unit
Max 12.0 12.0 12.0 6.4 2.9 2.9 6.0 6.0 6.0 7.8 30.0 12.0 12.0 12.0 30.0 30.0 ASYNC ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
4.0 4.0 4.0 0.0 0.6 0.6 3.0 3.0 3.0 3.0 10.0 4.0 4.0 4.0 10.0 10.0 ASYNC
Transmit High-Speed Signals
Receive Low-Speed Signals
Serial Control Interface (SCI)
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TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Timing Characteristics (continued)
Operational Timing (continued)
A diagram of the digital system interface timing for setup and hold time input as well as propagation delay output specifications are shown in Figure 17. The transmit and receive low-speed bus interfaces are shown in Figure 18.
CLOCK tSU DATA tH
CLOCK tPD DATA
5-5342(F)r.1
Figure 17. Interface Data Timing
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Data Sheet April 2001
Timing Characteristics (continued)
Operational Timing (continued)
TRANSMIT LOW-SPEED BUS INTERFACE SIGNALS
TLSCLKO
TLSSPEO
TLSJ0J1V1TIMEO
TLSV1TIMEO* A1 TLSDATA[7:0]I A2 J0 J1 V1
A1-1 A1-2 A1-3 A2-1 A2-2 A2-3 J0-1 J0-2 J0-3 J1-1 J1-2 J1-3 V1-1 V1-2 V1-3
3 bytes
3 bytes
3 bytes
3 bytes
3 bytes
RECEIVE LOW-SPEED BUS INTERFACE SIGNALS
RLSCLKO
RLSJ0TIMEO J0 RLSDATA[7:0]O
J0-1 J0-2 J0-3
3 bytes
5-6255(F)r.5
* V1 time occurs once every 500 s. J0 time occurs once per frame (125 s).
Figure 18. Bus Interface Signals
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Outline Diagram
208-Pin SQFP
Dimensions are in millimeters.
30.60 0.20 28.00 0.20 PIN #1 IDENTIFIER ZONE
208 157
1
156
28.00 0.20 30.60 0.20
52
105
53
104
DETAIL A
DETAIL B
3.40 0.20 4.10 MAX SEATING PLANE 0.08 0.25 MIN
0.50 TYP 1.30 REF
0.25 GAGE PLANE SEATING PLANE 0.50/0.75 0.17/0.27
0.090/0.200
0.10 DETAIL B
M
DETAIL A
5-2196(F)1.3r.14
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Data Sheet April 2001
Ordering Information
Device Code TMUX03155 Package 208-Pin SQFP Temperature -40 C to +85 C Comcode 108126368-DB
DS01-194PDH Replaces DS00-213TIC to Incorporate the Following Updates
I I I
Version 1 advisory (AY00-002SONT) information incorporated into the datasheet. Version ID register value changed to 3 (See Device Version and Device ID Number on page 29). For AU-4 mode, the B3 error count register (REI-P) mechanism was changed so that the transmit clock has enough time to sample the value for application on the outgoing G1[7:4] bits. The transitioning in the loss of pointer (LOP) state was fixed for the NDF condition.
I
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Data Sheet April 2001
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
Notes
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For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@micro.lucent.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Agere Systems (Shanghai) Co., Ltd., 33/F Jin Mao Tower, 88 Century Boulevard Pudong, Shanghai 200121 PRC Tel. (86) 21 50471212, FAX (86) 21 50472266 JAPAN: Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries:GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Copyright (c) 2001 Agere Systems Inc. All Rights Reserved Printed in U.S.A.
April 2001 DS01-194PDH (Replaces DS99-213TIC)

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